module MyDriver (in_v, out_v);
input [2:0] in_v;
wire[2:0] in_v;
output [6:0] out_v;
reg [6:0] out_v;
always @(in_v) 
begin
case(in_v)
0: out_v = 7'b0000001;
1: out_v = 7'b1001111;
2: out_v = 7'b0010010;
3: out_v = 7'b0000110;
4: out_v = 7'b1001100;
5: out_v = 7'b0100100;
6: out_v = 7'b0100000;
7: out_v = 7'b0001111;
endcase
end
endmodule