//priority encoder ( 4x2 )
module MyEncoder(i0,i1,i2,i3,en_out);
input i0,i1,i2,i3;
output [1:0] en_out;
reg [1:0] en_out;
always @ ( i0 or i1 or i2 or i3 )
	if(i3 == 1'b1)
	  en_out <= 2'b11;
	else if(i2 == 1'b1)
	  en_out <= 2'b10;
	else if(i1 == 1'b1)
	  en_out <= 2'b01;
	else 
	  en_out <= 2'b00;
endmodule 


//this will convert binary input 
// to 7-segment input
module sevenSegmentDriver(in_v , out_v ) ;
input [1:0] in_v ;
output [6:0] out_v ;
wire[1:0] in_v ;
reg [6:0] out_v ;
always @ (in_v) 
begin 
	case(in_v)
		0 : out_v = 7'b0000001;
		1 : out_v = 7'b1001111;
		2 : out_v = 7'b0010010;
		3 : out_v = 7'b0000110;
	endcase 
end
endmodule


module MyComp(CData,out);
input [6:0] CData;
wire [6:0] CData;
output out;
reg out;
always @ (CData)
begin
	//compare value in register with 2
	if(CData == 7'b0010010)
		out <=1'b1;
	else
		out <=1'b0;
	end
endmodule 




module D_Flip_Flop(Q,D, CLK);
     output Q;
     input D, CLK;
     reg Q;
     always @ (posedge CLK )
        Q=D;  
endmodule 


module MY_MUX(A, B, select, out);
	input A, B, select;
	output out;
	reg out;
	
always @(B or A or select)
	if (select == 0)
		out = B;
	else
		out = A;//new data
endmodule