Classic Timing Analyzer report for exp9
Wed May 12 17:56:33 2021
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                        ;
+------------------------------+-------+---------------+-------------+-----------------------------------------+------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From                                    ; To                                       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------------------------------------+------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 5.459 ns    ; 2                                       ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.990 ns    ; Memory_System:inst2|D_Flip_Flop:inst8|Q ; true_GREEN                               ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.260 ns   ; 1                                       ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; --         ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;             ;                                         ;                                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-----------------------------------------+------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------+
; tsu                                                                                              ;
+-------+--------------+------------+--------+------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To                                       ; To Clock ;
+-------+--------------+------------+--------+------------------------------------------+----------+
; N/A   ; None         ; 5.459 ns   ; 2      ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; clk      ;
; N/A   ; None         ; 5.191 ns   ; 2      ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 4.965 ns   ; 2      ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 4.962 ns   ; 2      ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A   ; None         ; 4.812 ns   ; 2      ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 4.665 ns   ; 3      ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; clk      ;
; N/A   ; None         ; 4.638 ns   ; 3      ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 4.353 ns   ; 2      ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 4.350 ns   ; 1      ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 4.350 ns   ; 2      ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 4.349 ns   ; 2      ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; clk      ;
; N/A   ; None         ; 4.349 ns   ; 2      ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 4.348 ns   ; 2      ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A   ; None         ; 4.325 ns   ; 3      ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 4.262 ns   ; 3      ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 4.166 ns   ; 3      ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A   ; None         ; 4.159 ns   ; 1      ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 4.009 ns   ; 1      ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 3.803 ns   ; enable ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A   ; None         ; 3.800 ns   ; 3      ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 3.796 ns   ; 3      ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A   ; None         ; 3.713 ns   ; 3      ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 3.555 ns   ; 3      ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; clk      ;
; N/A   ; None         ; 3.552 ns   ; 3      ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A   ; None         ; 3.547 ns   ; 1      ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A   ; None         ; 3.547 ns   ; 1      ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A   ; None         ; 3.508 ns   ; 1      ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
+-------+--------------+------------+--------+------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------+
; tco                                                                                                    ;
+-------+--------------+------------+------------------------------------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From                                     ; To         ; From Clock ;
+-------+--------------+------------+------------------------------------------+------------+------------+
; N/A   ; None         ; 8.990 ns   ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.942 ns   ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.922 ns   ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.728 ns   ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; false_RED  ; clk        ;
; N/A   ; None         ; 8.680 ns   ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 8.660 ns   ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 8.521 ns   ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.441 ns   ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.354 ns   ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.279 ns   ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.263 ns   ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 8.259 ns   ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 8.179 ns   ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 8.092 ns   ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 8.017 ns   ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 8.001 ns   ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; false_RED  ; clk        ;
; N/A   ; None         ; 7.961 ns   ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; true_GREEN ; clk        ;
; N/A   ; None         ; 7.699 ns   ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; false_RED  ; clk        ;
; N/A   ; None         ; 7.489 ns   ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; true_GREEN ; clk        ;
; N/A   ; None         ; 7.227 ns   ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; false_RED  ; clk        ;
+-------+--------------+------------+------------------------------------------+------------+------------+


+--------------------------------------------------------------------------------------------------------+
; th                                                                                                     ;
+---------------+-------------+-----------+--------+------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                                       ; To Clock ;
+---------------+-------------+-----------+--------+------------------------------------------+----------+
; N/A           ; None        ; -3.260 ns ; 1      ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -3.299 ns ; 1      ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -3.299 ns ; 1      ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -3.304 ns ; 3      ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A           ; None        ; -3.307 ns ; 3      ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; clk      ;
; N/A           ; None        ; -3.465 ns ; 3      ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -3.548 ns ; 3      ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -3.552 ns ; 3      ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -3.555 ns ; enable ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A           ; None        ; -3.761 ns ; 1      ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -3.911 ns ; 1      ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -3.918 ns ; 3      ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A           ; None        ; -4.014 ns ; 3      ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -4.077 ns ; 3      ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -4.100 ns ; 2      ; Memory_System:inst2|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A           ; None        ; -4.101 ns ; 2      ; Memory_System:inst2|D_Flip_Flop:inst16|Q ; clk      ;
; N/A           ; None        ; -4.101 ns ; 2      ; Memory_System:inst2|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -4.102 ns ; 1      ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -4.102 ns ; 2      ; Memory_System:inst2|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -4.105 ns ; 2      ; Memory_System:inst2|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -4.390 ns ; 3      ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -4.417 ns ; 3      ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; clk      ;
; N/A           ; None        ; -4.564 ns ; 2      ; Memory_System:inst3|D_Flip_Flop:inst12|Q ; clk      ;
; N/A           ; None        ; -4.714 ns ; 2      ; Memory_System:inst3|D_Flip_Flop:inst8|Q  ; clk      ;
; N/A           ; None        ; -4.717 ns ; 2      ; Memory_System:inst3|D_Flip_Flop:inst20|Q ; clk      ;
; N/A           ; None        ; -4.943 ns ; 2      ; Memory_System:inst3|D_Flip_Flop:inst10|Q ; clk      ;
; N/A           ; None        ; -5.211 ns ; 2      ; Memory_System:inst3|D_Flip_Flop:inst16|Q ; clk      ;
+---------------+-------------+-----------+--------+------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Wed May 12 17:56:32 2021
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off exp9 -c exp9 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "Memory_System:inst3|D_Flip_Flop:inst16|Q" (data pin = "2", clock pin = "clk") is 5.459 ns
    Info: + Longest pin to register delay is 8.360 ns
        Info: 1: + IC(0.000 ns) + CELL(0.863 ns) = 0.863 ns; Loc. = PIN_A10; Fanout = 5; PIN Node = '2'
        Info: 2: + IC(6.113 ns) + CELL(0.178 ns) = 7.154 ns; Loc. = LCCOMB_X4_Y25_N8; Fanout = 2; COMB Node = 'sevenSegmentDriver:inst1|Decoder0~0'
        Info: 3: + IC(0.793 ns) + CELL(0.413 ns) = 8.360 ns; Loc. = LCFF_X4_Y25_N27; Fanout = 1; REG Node = 'Memory_System:inst3|D_Flip_Flop:inst16|Q'
        Info: Total cell delay = 1.454 ns ( 17.39 % )
        Info: Total interconnect delay = 6.906 ns ( 82.61 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.863 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.997 ns) + CELL(0.602 ns) = 2.863 ns; Loc. = LCFF_X4_Y25_N27; Fanout = 1; REG Node = 'Memory_System:inst3|D_Flip_Flop:inst16|Q'
        Info: Total cell delay = 1.628 ns ( 56.86 % )
        Info: Total interconnect delay = 1.235 ns ( 43.14 % )
Info: tco from clock "clk" to destination pin "true_GREEN" through register "Memory_System:inst2|D_Flip_Flop:inst8|Q" is 8.990 ns
    Info: + Longest clock path from clock "clk" to source register is 2.863 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.997 ns) + CELL(0.602 ns) = 2.863 ns; Loc. = LCFF_X4_Y25_N5; Fanout = 1; REG Node = 'Memory_System:inst2|D_Flip_Flop:inst8|Q'
        Info: Total cell delay = 1.628 ns ( 56.86 % )
        Info: Total interconnect delay = 1.235 ns ( 43.14 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 5.850 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y25_N5; Fanout = 1; REG Node = 'Memory_System:inst2|D_Flip_Flop:inst8|Q'
        Info: 2: + IC(0.630 ns) + CELL(0.455 ns) = 1.085 ns; Loc. = LCCOMB_X4_Y25_N26; Fanout = 1; COMB Node = 'inst6~1'
        Info: 3: + IC(0.289 ns) + CELL(0.485 ns) = 1.859 ns; Loc. = LCCOMB_X4_Y25_N18; Fanout = 2; COMB Node = 'inst6~2'
        Info: 4: + IC(0.975 ns) + CELL(3.016 ns) = 5.850 ns; Loc. = PIN_A4; Fanout = 0; PIN Node = 'true_GREEN'
        Info: Total cell delay = 3.956 ns ( 67.62 % )
        Info: Total interconnect delay = 1.894 ns ( 32.38 % )
Info: th for register "Memory_System:inst2|D_Flip_Flop:inst10|Q" (data pin = "1", clock pin = "clk") is -3.260 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.863 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.997 ns) + CELL(0.602 ns) = 2.863 ns; Loc. = LCFF_X4_Y25_N11; Fanout = 1; REG Node = 'Memory_System:inst2|D_Flip_Flop:inst10|Q'
        Info: Total cell delay = 1.628 ns ( 56.86 % )
        Info: Total interconnect delay = 1.235 ns ( 43.14 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 6.409 ns
        Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_E3; Fanout = 3; PIN Node = '1'
        Info: 2: + IC(5.171 ns) + CELL(0.278 ns) = 6.313 ns; Loc. = LCCOMB_X4_Y25_N10; Fanout = 2; COMB Node = 'sevenSegmentDriver:inst1|Decoder0~1'
        Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.409 ns; Loc. = LCFF_X4_Y25_N11; Fanout = 1; REG Node = 'Memory_System:inst2|D_Flip_Flop:inst10|Q'
        Info: Total cell delay = 1.238 ns ( 19.32 % )
        Info: Total interconnect delay = 5.171 ns ( 80.68 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 179 megabytes
    Info: Processing ended: Wed May 12 17:56:33 2021
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


