Analysis & Synthesis report for ENCS234_Project
Fri Jul 03 23:43:01 2020
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Multiplexer Restructuring Statistics (Restructuring Performed)
  9. Port Connectivity Checks: "bcd_adder:inst8|add_sub_4:FA2"
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                            ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status   ; Successful - Fri Jul 03 23:43:01 2020   ;
; Quartus II Version            ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name                 ; ENCS234_Project                         ;
; Top-level Entity Name         ; ENCS234_Project                         ;
; Family                        ; Stratix II                              ;
; Logic utilization             ; N/A                                     ;
;     Combinational ALUTs       ; 15                                      ;
;     Dedicated logic registers ; 0                                       ;
; Total registers               ; 0                                       ;
; Total pins                    ; 17                                      ;
; Total virtual pins            ; 0                                       ;
; Total block memory bits       ; 0                                       ;
; DSP block 9-bit elements      ; 0                                       ;
; Total PLLs                    ; 0                                       ;
; Total DLLs                    ; 0                                       ;
+-------------------------------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                            ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option                                                         ; Setting            ; Default Value      ;
+----------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                          ; ENCS234_Project    ; ENCS234_Project    ;
; Family name                                                    ; Stratix II         ; Stratix II         ;
; Use Generated Physical Constraints File                        ; Off                ;                    ;
; Use smart compilation                                          ; Off                ; Off                ;
; Restructure Multiplexers                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                            ; Off                ; Off                ;
; Preserve fewer node names                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                      ; Off                ; Off                ;
; Verilog Version                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                       ; Auto               ; Auto               ;
; Safe State Machine                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                              ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                     ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                 ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                        ; On                 ; On                 ;
; Parallel Synthesis                                             ; Off                ; Off                ;
; DSP Block Balancing                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                             ; On                 ; On                 ;
; Power-Up Don't Care                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                 ; Off                ; Off                ;
; Optimization Technique                                         ; Balanced           ; Balanced           ;
; Carry Chain Length                                             ; 70                 ; 70                 ;
; Auto Carry Chains                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                          ; Off                ; Off                ;
; Auto ROM Replacement                                           ; On                 ; On                 ;
; Auto RAM Replacement                                           ; On                 ; On                 ;
; Auto DSP Block Replacement                                     ; On                 ; On                 ;
; Auto Shift Register Replacement                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                  ; On                 ; On                 ;
; Strict RAM Replacement                                         ; Off                ; Off                ;
; Allow Synchronous Control Signals                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                              ; Off                ; Off                ;
; Auto Resource Sharing                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                  ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing            ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives              ; Off                ; Off                ;
; Timing-Driven Synthesis                                        ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                             ; Off                ; Off                ;
; Synchronization Register Chain Length                          ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report       ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report      ; 100                ; 100                ;
; Clock MUX Protection                                           ; On                 ; On                 ;
; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                         ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------+
; full_adder1.v                    ; yes             ; User Verilog HDL File              ; C:/Users/Toshiba/Desktop/Project/full_adder1.v       ;
; add_sub_4.v                      ; yes             ; User Verilog HDL File              ; C:/Users/Toshiba/Desktop/Project/add_sub_4.v         ;
; Max.v                            ; yes             ; User Verilog HDL File              ; C:/Users/Toshiba/Desktop/Project/Max.v               ;
; bcd_adder.v                      ; yes             ; User Verilog HDL File              ; C:/Users/Toshiba/Desktop/Project/bcd_adder.v         ;
; Min.v                            ; yes             ; User Verilog HDL File              ; C:/Users/Toshiba/Desktop/Project/Min.v               ;
; Muxx.v                           ; yes             ; User Verilog HDL File              ; C:/Users/Toshiba/Desktop/Project/Muxx.v              ;
; ENCS234_Project.bdf              ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Toshiba/Desktop/Project/ENCS234_Project.bdf ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 15    ;
; Dedicated logic registers                     ; 0     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 3     ;
;                                               ;       ;
; Total combinational functions                 ; 15    ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 6     ;
;     -- 5 input functions                      ; 3     ;
;     -- 4 input functions                      ; 5     ;
;     -- <=3 input functions                    ; 1     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 15    ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 15    ;
;                                               ;       ;
; Total registers                               ; 0     ;
;     -- Dedicated logic registers              ; 0     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 8     ;
;                                               ;       ;
; I/O pins                                      ; 17    ;
; Maximum fan-out node                          ; S[1]  ;
; Maximum fan-out                               ; 6     ;
; Total fan-out                                 ; 80    ;
; Average fan-out                               ; 2.50  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                     ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                           ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------+--------------+
; |ENCS234_Project           ; 15 (0)            ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 17   ; 0            ; |ENCS234_Project                                              ; work         ;
;    |Muxx:inst7|            ; 8 (8)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|Muxx:inst7                                   ; work         ;
;    |bcd_adder:inst8|       ; 7 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8                              ; work         ;
;       |add_sub_4:FA1|      ; 5 (0)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8|add_sub_4:FA1                ; work         ;
;          |full_adder1:f6|  ; 2 (2)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8|add_sub_4:FA1|full_adder1:f6 ; work         ;
;          |full_adder1:f7|  ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8|add_sub_4:FA1|full_adder1:f7 ; work         ;
;          |full_adder1:f8|  ; 2 (2)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8|add_sub_4:FA1|full_adder1:f8 ; work         ;
;       |add_sub_4:FA2|      ; 1 (0)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8|add_sub_4:FA2                ; work         ;
;          |full_adder1:f7|  ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ENCS234_Project|bcd_adder:inst8|add_sub_4:FA2|full_adder1:f7 ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; 6:1                ; 3 bits    ; 12 ALUTs      ; 6 ALUTs              ; 6 ALUTs                ; No         ; |ENCS234_Project|Muxx:inst7|out[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "bcd_adder:inst8|add_sub_4:FA2"                                                       ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; C_out ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Fri Jul 03 23:42:59 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ENCS234_Project -c ENCS234_Project
Info: Found 1 design units, including 1 entities, in source file full_adder1.v
    Info: Found entity 1: full_adder1
Info: Found 1 design units, including 1 entities, in source file add_sub_4.v
    Info: Found entity 1: add_sub_4
Info: Found 1 design units, including 1 entities, in source file Max.v
    Info: Found entity 1: Max
Info: Found 1 design units, including 1 entities, in source file bcd_adder.v
    Info: Found entity 1: bcd_adder
Info: Found 1 design units, including 1 entities, in source file Min.v
    Info: Found entity 1: Min
Info: Found 1 design units, including 1 entities, in source file Muxx.v
    Info: Found entity 1: Muxx
Info: Found 1 design units, including 1 entities, in source file ENCS234_Project.bdf
    Info: Found entity 1: ENCS234_Project
Info: Elaborating entity "ENCS234_Project" for the top level hierarchy
Info: Elaborating entity "bcd_adder" for hierarchy "bcd_adder:inst8"
Info: Elaborating entity "add_sub_4" for hierarchy "bcd_adder:inst8|add_sub_4:FA1"
Info: Elaborating entity "full_adder1" for hierarchy "bcd_adder:inst8|add_sub_4:FA1|full_adder1:f5"
Info: Elaborating entity "Muxx" for hierarchy "Muxx:inst7"
Info: Elaborating entity "Max" for hierarchy "Max:inst9"
Info: Elaborating entity "Min" for hierarchy "Min:inst10"
Warning: Net is missing source, defaulting to GND
    Warning (12110): Net "bcd_adder:inst8|six[0]" is missing source, defaulting to GND
Info: Ignored 2 buffer(s)
    Info: Ignored 2 SOFT buffer(s)
Info: Implemented 32 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 6 output pins
    Info: Implemented 15 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 221 megabytes
    Info: Processing ended: Fri Jul 03 23:43:01 2020
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


