Classic Timing Analyzer report for ENCS234_Project
Wed Jul 01 16:25:23 2020
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To  ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.206 ns   ; A    ; Sum ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;     ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To    ;
+-------+-------------------+-----------------+------+-------+
; N/A   ; None              ; 10.206 ns       ; A    ; Sum   ;
; N/A   ; None              ; 9.499 ns        ; Cin  ; Sum   ;
; N/A   ; None              ; 9.071 ns        ; B    ; Sum   ;
; N/A   ; None              ; 8.934 ns        ; A    ; C_out ;
; N/A   ; None              ; 8.227 ns        ; Cin  ; C_out ;
; N/A   ; None              ; 7.800 ns        ; B    ; C_out ;
+-------+-------------------+-----------------+------+-------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Wed Jul 01 16:25:22 2020
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ENCS234_Project -c ENCS234_Project --timing_analysis_only
Info: Longest tpd from source pin "A" to destination pin "Sum" is 10.206 ns
    Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AA11; Fanout = 2; PIN Node = 'A'
    Info: 2: + IC(4.706 ns) + CELL(0.366 ns) = 5.881 ns; Loc. = LCCOMB_X15_Y18_N18; Fanout = 1; COMB Node = 'xor2'
    Info: 3: + IC(2.171 ns) + CELL(2.154 ns) = 10.206 ns; Loc. = PIN_F1; Fanout = 0; PIN Node = 'Sum'
    Info: Total cell delay = 3.329 ns ( 32.62 % )
    Info: Total interconnect delay = 6.877 ns ( 67.38 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 187 megabytes
    Info: Processing ended: Wed Jul 01 16:25:23 2020
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


