{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 30 23:52:45 2010 " "Info: Processing started: Tue Mar 30 23:52:45 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MyMemory -c MyMemory " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MyMemory -c MyMemory" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyMemory.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyMemory.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 MyMemory " "Info: Found entity 1: MyMemory" {  } { { "MyMemory.bdf" "" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/Memory System/MyMemory.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"(\";  expecting \";\", or \",\" MyMemory.v(20) " "Error (10170): Verilog HDL syntax error at MyMemory.v(20) near text \"(\";  expecting \";\", or \",\"" {  } { { "MyMemory.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/Memory System/MyMemory.v" 20 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_FEATURE_REQUIRES_SV" "declaring global objects MyMemory.v(19) " "Error (10839): Verilog HDL error at MyMemory.v(19): declaring global objects is a SystemVerilog feature" {  } { { "MyMemory.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/Memory System/MyMemory.v" 19 0 0 } }  } 0 10839 "Verilog HDL error at %2!s!: %1!s! is a SystemVerilog feature" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyMemory.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file MyMemory.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Error: Peak virtual memory: 192 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 30 23:52:47 2010 " "Error: Processing ended: Tue Mar 30 23:52:47 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Error: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
