Version 9.0 Build 132 02/25/2009 SJ Web Edition
11
980
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
alu
# storage
db|alu.(0).cnf
db|alu.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
alu.v
116e1949d1fc3934b7e5f942b538748
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
lpm_mult
# storage
db|alu.(1).cnf
db|alu.(1).cnf
# case_insensitive
# source_file
c:|altera|90|quartus|libraries|megafunctions|lpm_mult.tdf
b9c65dc812b19c0df9dff1b77e14a
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
4
PARAMETER_UNKNOWN
USR
LPM_WIDTHB
4
PARAMETER_UNKNOWN
USR
LPM_WIDTHP
8
PARAMETER_UNKNOWN
USR
LPM_WIDTHR
8
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
LUT
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
USR
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_lq01
PARAMETER_UNKNOWN
USR
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
USE_AHDL_IMPLEMENTATION
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# include_file {
c:|altera|90|quartus|libraries|megafunctions|aglobal90.inc
99832fdf63412df51d7531202d74e75
c:|altera|90|quartus|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
c:|altera|90|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
c:|altera|90|quartus|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
c:|altera|90|quartus|libraries|megafunctions|multcore.inc
13b7e8bee916e23c5f79837e9c670
}
# macro_sequence

# end
# entity
mult_lq01
# storage
db|alu.(2).cnf
db|alu.(2).cnf
# case_insensitive
# source_file
db|mult_lq01.tdf
741ef6c8954b3bfb469ef48ad4616ad
7
# used_port {
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# macro_sequence

# end
# complete

