{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 16:33:56 2010 " "Info: Processing started: Wed Mar 24 16:33:56 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off all -c all --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off all -c all --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "all.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file all.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 all " "Info: Found entity 1: all" {  } { { "all.bdf" "" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/all.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "all " "Info: Elaborating entity \"all\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "sevenseg.v 1 1 " "Warning: Using design file sevenseg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sevenseg " "Info: Found entity 1: sevenseg" {  } { { "sevenseg.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/sevenseg.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "sevenseg " "Warning (12300): Found the following files while searching for definition of entity \"sevenseg\", but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "sevenseg.bdf " "Warning: File: sevenseg.bdf" {  } {  } 0 0 "File: %1!s!" 0 0 "" 0 -1}  } {  } 0 12300 "Found the following files while searching for definition of entity \"%1!s!\", but did not use these files because already using a different file containing the entity definition" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sevenseg sevenseg:inst2 " "Info: Elaborating entity \"sevenseg\" for hierarchy \"sevenseg:inst2\"" {  } { { "all.bdf" "inst2" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/all.bdf" { { 56 488 616 152 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "counter.v 1 1 " "Warning: Using design file counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/counter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst1\"" {  } { { "all.bdf" "inst1" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/all.bdf" { { 56 312 440 152 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(16) " "Warning (10230): Verilog HDL assignment warning at counter.v(16): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/counter.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(17) " "Warning (10230): Verilog HDL assignment warning at counter.v(17): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/counter.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "freq_div.v 1 1 " "Warning: Using design file freq_div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 freq_div " "Info: Found entity 1: freq_div" {  } { { "freq_div.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/freq_div.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq_div freq_div:inst " "Info: Elaborating entity \"freq_div\" for hierarchy \"freq_div:inst\"" {  } { { "all.bdf" "inst" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/all.bdf" { { 56 160 256 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 freq_div.v(24) " "Warning (10230): Verilog HDL assignment warning at freq_div.v(24): truncated value with size 32 to match size of target (3)" {  } { { "freq_div.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/All/freq_div.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 8 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "190 " "Info: Peak virtual memory: 190 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 16:33:58 2010 " "Info: Processing ended: Wed Mar 24 16:33:58 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
