{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 15:19:28 2012 " "Info: Processing started: Wed Nov 21 15:19:28 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Exp9 -c Exp9 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Exp9 -c Exp9" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MYEncoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MYEncoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 MYEncoder " "Info: Found entity 1: MYEncoder" {  } { { "MYEncoder.v" "" { Text "G:/Exp9/MYEncoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "MyDecoder.v(7) " "Warning (10268): Verilog HDL information at MyDecoder.v(7): always construct contains both blocking and non-blocking assignments" {  } { { "MyDecoder.v" "" { Text "G:/Exp9/MyDecoder.v" 7 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyDecoder " "Info: Found entity 1: MyDecoder" {  } { { "MyDecoder.v" "" { Text "G:/Exp9/MyDecoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDriver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDriver.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyDriver " "Info: Found entity 1: MyDriver" {  } { { "MyDriver.v" "" { Text "G:/Exp9/MyDriver.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyMUX.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyMUX.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyMUX " "Info: Found entity 1: MyMUX" {  } { { "MyMUX.v" "" { Text "G:/Exp9/MyMUX.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDFF.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDFF.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyDFF " "Info: Found entity 1: MyDFF" {  } { { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyComp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyComp.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyComp " "Info: Found entity 1: MyComp" {  } { { "MyComp.v" "" { Text "G:/Exp9/MyComp.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyMemory.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyMemory.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 MyMemory " "Info: Found entity 1: MyMemory" {  } { { "MyMemory.bdf" "" { Schematic "G:/Exp9/MyMemory.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Exp9.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Exp9.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Exp9 " "Info: Found entity 1: Exp9" {  } { { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyComp2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyComp2.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyComp2 " "Info: Found entity 1: MyComp2" {  } { { "MyComp2.v" "" { Text "G:/Exp9/MyComp2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "Exp9 " "Info: Elaborating entity \"Exp9\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyComp MyComp:inst4 " "Info: Elaborating entity \"MyComp\" for hierarchy \"MyComp:inst4\"" {  } { { "Exp9.bdf" "inst4" { Schematic "G:/Exp9/Exp9.bdf" { { 48 168 264 168 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyMemory MyMemory:inst " "Info: Elaborating entity \"MyMemory\" for hierarchy \"MyMemory:inst\"" {  } { { "Exp9.bdf" "inst" { Schematic "G:/Exp9/Exp9.bdf" { { 216 168 360 352 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyDFF MyMemory:inst\|MyDFF:inst11 " "Info: Elaborating entity \"MyDFF\" for hierarchy \"MyMemory:inst\|MyDFF:inst11\"" {  } { { "MyMemory.bdf" "inst11" { Schematic "G:/Exp9/MyMemory.bdf" { { 72 752 848 168 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyMUX MyMemory:inst\|MyMUX:inst4 " "Info: Elaborating entity \"MyMUX\" for hierarchy \"MyMemory:inst\|MyMUX:inst4\"" {  } { { "MyMemory.bdf" "inst4" { Schematic "G:/Exp9/MyMemory.bdf" { { 304 744 840 400 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyDriver MyDriver:inst17 " "Info: Elaborating entity \"MyDriver\" for hierarchy \"MyDriver:inst17\"" {  } { { "Exp9.bdf" "inst17" { Schematic "G:/Exp9/Exp9.bdf" { { 720 848 1000 816 "inst17" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MYEncoder MYEncoder:inst10 " "Info: Elaborating entity \"MYEncoder\" for hierarchy \"MYEncoder:inst10\"" {  } { { "Exp9.bdf" "inst10" { Schematic "G:/Exp9/Exp9.bdf" { { 720 600 720 912 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyDecoder MyDecoder:inst8 " "Info: Elaborating entity \"MyDecoder\" for hierarchy \"MyDecoder:inst8\"" {  } { { "Exp9.bdf" "inst8" { Schematic "G:/Exp9/Exp9.bdf" { { 712 168 264 864 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "en MyDecoder.v(9) " "Warning (10235): Verilog HDL Always Construct warning at MyDecoder.v(9): variable \"en\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "MyDecoder.v" "" { Text "G:/Exp9/MyDecoder.v" 9 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyComp2 MyComp2:inst1 " "Info: Elaborating entity \"MyComp2\" for hierarchy \"MyComp2:inst1\"" {  } { { "Exp9.bdf" "inst1" { Schematic "G:/Exp9/Exp9.bdf" { { 32 440 536 152 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Exp9/Exp9.map.smsg " "Info: Generated suppressed messages file G:/Exp9/Exp9.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "i0 " "Warning (15610): No output dependent on input pin \"i0\"" {  } { { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 920 320 488 936 "i0" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "dis " "Warning (15610): No output dependent on input pin \"dis\"" {  } { { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 1160 320 488 1176 "dis" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "88 " "Info: Implemented 88 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Info: Implemented 30 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "200 " "Info: Peak virtual memory: 200 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 15:19:40 2012 " "Info: Processing ended: Wed Nov 21 15:19:40 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 15:19:42 2012 " "Info: Processing started: Wed Nov 21 15:19:42 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Exp9 -c Exp9 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Exp9 -c Exp9" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "Exp9 EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"Exp9\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is not available with your current license" {  } {  } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 42 " "Warning: No exact pin location assignment(s) for 1 pins of 42 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "dis " "Info: Pin dis not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { dis } } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 1160 320 488 1176 "dis" "" } } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { dis } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN D12 (CLK10, LVDSCLK5n, Input)) " "Info: Automatically promoted node CLK (placed in PIN D12 (CLK10, LVDSCLK5n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G11 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { CLK } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 1 0 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 31 2 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used --  2 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 42 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 2 37 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  37 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 4 32 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 4 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 2 38 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  38 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 2 41 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y14 X11_Y27 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "30 " "Warning: Found 30 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "red 0 " "Info: Pin \"red\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "green 0 " "Info: Pin \"green\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[6\] 0 " "Info: Pin \"DIS1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[5\] 0 " "Info: Pin \"DIS1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[4\] 0 " "Info: Pin \"DIS1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[3\] 0 " "Info: Pin \"DIS1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[2\] 0 " "Info: Pin \"DIS1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[1\] 0 " "Info: Pin \"DIS1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS1\[0\] 0 " "Info: Pin \"DIS1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[6\] 0 " "Info: Pin \"DIS2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[5\] 0 " "Info: Pin \"DIS2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[4\] 0 " "Info: Pin \"DIS2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[3\] 0 " "Info: Pin \"DIS2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[2\] 0 " "Info: Pin \"DIS2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[1\] 0 " "Info: Pin \"DIS2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS2\[0\] 0 " "Info: Pin \"DIS2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[6\] 0 " "Info: Pin \"DIS3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[5\] 0 " "Info: Pin \"DIS3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[4\] 0 " "Info: Pin \"DIS3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[3\] 0 " "Info: Pin \"DIS3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[2\] 0 " "Info: Pin \"DIS3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[1\] 0 " "Info: Pin \"DIS3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS3\[0\] 0 " "Info: Pin \"DIS3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[6\] 0 " "Info: Pin \"DIS4\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[5\] 0 " "Info: Pin \"DIS4\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[4\] 0 " "Info: Pin \"DIS4\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[3\] 0 " "Info: Pin \"DIS4\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[2\] 0 " "Info: Pin \"DIS4\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[1\] 0 " "Info: Pin \"DIS4\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DIS4\[0\] 0 " "Info: Pin \"DIS4\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 15:19:53 2012 " "Info: Processing ended: Wed Nov 21 15:19:53 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 15:19:55 2012 " "Info: Processing started: Wed Nov 21 15:19:55 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Exp9 -c Exp9 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Exp9 -c Exp9" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 15:20:13 2012 " "Info: Processing ended: Wed Nov 21 15:20:13 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 15:20:16 2012 " "Info: Processing started: Wed Nov 21 15:20:16 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Exp9 -c Exp9 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Exp9 -c Exp9 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "MyMemory:inst\|MyDFF:inst14\|Q i2 CLK 4.548 ns register " "Info: tsu for register \"MyMemory:inst\|MyDFF:inst14\|Q\" (data pin = \"i2\", clock pin = \"CLK\") is 4.548 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.396 ns + Longest pin register " "Info: + Longest pin to register delay is 7.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns i2 1 PIN PIN_M22 3 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_M22; Fanout = 3; PIN Node = 'i2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2 } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 984 320 488 1000 "i2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.029 ns) + CELL(0.457 ns) 3.522 ns MYEncoder:inst10\|en_out\[0\]~11 2 COMB LCCOMB_X20_Y20_N16 1 " "Info: 2: + IC(2.029 ns) + CELL(0.457 ns) = 3.522 ns; Loc. = LCCOMB_X20_Y20_N16; Fanout = 1; COMB Node = 'MYEncoder:inst10\|en_out\[0\]~11'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.486 ns" { i2 MYEncoder:inst10|en_out[0]~11 } "NODE_NAME" } } { "MYEncoder.v" "" { Text "G:/Exp9/MYEncoder.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.842 ns) + CELL(0.178 ns) 5.542 ns MYEncoder:inst10\|en_out\[0\]~12 3 COMB LCCOMB_X2_Y20_N16 4 " "Info: 3: + IC(1.842 ns) + CELL(0.178 ns) = 5.542 ns; Loc. = LCCOMB_X2_Y20_N16; Fanout = 4; COMB Node = 'MYEncoder:inst10\|en_out\[0\]~12'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.020 ns" { MYEncoder:inst10|en_out[0]~11 MYEncoder:inst10|en_out[0]~12 } "NODE_NAME" } } { "MYEncoder.v" "" { Text "G:/Exp9/MYEncoder.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.322 ns) 6.189 ns MyDriver:inst17\|out_v\[6\]~3 4 COMB LCCOMB_X2_Y20_N8 4 " "Info: 4: + IC(0.325 ns) + CELL(0.322 ns) = 6.189 ns; Loc. = LCCOMB_X2_Y20_N8; Fanout = 4; COMB Node = 'MyDriver:inst17\|out_v\[6\]~3'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.647 ns" { MYEncoder:inst10|en_out[0]~12 MyDriver:inst17|out_v[6]~3 } "NODE_NAME" } } { "MyDriver.v" "" { Text "G:/Exp9/MyDriver.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(0.413 ns) 7.396 ns MyMemory:inst\|MyDFF:inst14\|Q 5 REG LCFF_X2_Y20_N5 3 " "Info: 5: + IC(0.794 ns) + CELL(0.413 ns) = 7.396 ns; Loc. = LCFF_X2_Y20_N5; Fanout = 3; REG Node = 'MyMemory:inst\|MyDFF:inst14\|Q'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.207 ns" { MyDriver:inst17|out_v[6]~3 MyMemory:inst|MyDFF:inst14|Q } "NODE_NAME" } } { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.406 ns ( 32.53 % ) " "Info: Total cell delay = 2.406 ns ( 32.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.990 ns ( 67.47 % ) " "Info: Total interconnect delay = 4.990 ns ( 67.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.396 ns" { i2 MYEncoder:inst10|en_out[0]~11 MYEncoder:inst10|en_out[0]~12 MyDriver:inst17|out_v[6]~3 MyMemory:inst|MyDFF:inst14|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.396 ns" { i2 {} i2~combout {} MYEncoder:inst10|en_out[0]~11 {} MYEncoder:inst10|en_out[0]~12 {} MyDriver:inst17|out_v[6]~3 {} MyMemory:inst|MyDFF:inst14|Q {} } { 0.000ns 0.000ns 2.029ns 1.842ns 0.325ns 0.794ns } { 0.000ns 1.036ns 0.457ns 0.178ns 0.322ns 0.413ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.810 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns CLK 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns CLK~clkctrl 2 COMB CLKCTRL_G11 24 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 24; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.964 ns) + CELL(0.602 ns) 2.810 ns MyMemory:inst\|MyDFF:inst14\|Q 3 REG LCFF_X2_Y20_N5 3 " "Info: 3: + IC(0.964 ns) + CELL(0.602 ns) = 2.810 ns; Loc. = LCFF_X2_Y20_N5; Fanout = 3; REG Node = 'MyMemory:inst\|MyDFF:inst14\|Q'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { CLK~clkctrl MyMemory:inst|MyDFF:inst14|Q } "NODE_NAME" } } { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 57.22 % ) " "Info: Total cell delay = 1.608 ns ( 57.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.202 ns ( 42.78 % ) " "Info: Total interconnect delay = 1.202 ns ( 42.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { CLK CLK~clkctrl MyMemory:inst|MyDFF:inst14|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { CLK {} CLK~combout {} CLK~clkctrl {} MyMemory:inst|MyDFF:inst14|Q {} } { 0.000ns 0.000ns 0.238ns 0.964ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.396 ns" { i2 MYEncoder:inst10|en_out[0]~11 MYEncoder:inst10|en_out[0]~12 MyDriver:inst17|out_v[6]~3 MyMemory:inst|MyDFF:inst14|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.396 ns" { i2 {} i2~combout {} MYEncoder:inst10|en_out[0]~11 {} MYEncoder:inst10|en_out[0]~12 {} MyDriver:inst17|out_v[6]~3 {} MyMemory:inst|MyDFF:inst14|Q {} } { 0.000ns 0.000ns 2.029ns 1.842ns 0.325ns 0.794ns } { 0.000ns 1.036ns 0.457ns 0.178ns 0.322ns 0.413ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { CLK CLK~clkctrl MyMemory:inst|MyDFF:inst14|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { CLK {} CLK~combout {} CLK~clkctrl {} MyMemory:inst|MyDFF:inst14|Q {} } { 0.000ns 0.000ns 0.238ns 0.964ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK red MyMemory:inst\|MyDFF:inst13\|Q 14.389 ns register " "Info: tco from clock \"CLK\" to destination pin \"red\" through register \"MyMemory:inst\|MyDFF:inst13\|Q\" is 14.389 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.810 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns CLK 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns CLK~clkctrl 2 COMB CLKCTRL_G11 24 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 24; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.964 ns) + CELL(0.602 ns) 2.810 ns MyMemory:inst\|MyDFF:inst13\|Q 3 REG LCFF_X2_Y20_N11 2 " "Info: 3: + IC(0.964 ns) + CELL(0.602 ns) = 2.810 ns; Loc. = LCFF_X2_Y20_N11; Fanout = 2; REG Node = 'MyMemory:inst\|MyDFF:inst13\|Q'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { CLK~clkctrl MyMemory:inst|MyDFF:inst13|Q } "NODE_NAME" } } { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 57.22 % ) " "Info: Total cell delay = 1.608 ns ( 57.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.202 ns ( 42.78 % ) " "Info: Total interconnect delay = 1.202 ns ( 42.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { CLK CLK~clkctrl MyMemory:inst|MyDFF:inst13|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { CLK {} CLK~combout {} CLK~clkctrl {} MyMemory:inst|MyDFF:inst13|Q {} } { 0.000ns 0.000ns 0.238ns 0.964ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.302 ns + Longest register pin " "Info: + Longest register to pin delay is 11.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MyMemory:inst\|MyDFF:inst13\|Q 1 REG LCFF_X2_Y20_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y20_N11; Fanout = 2; REG Node = 'MyMemory:inst\|MyDFF:inst13\|Q'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MyMemory:inst|MyDFF:inst13|Q } "NODE_NAME" } } { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.507 ns) 0.890 ns inst21~0 2 COMB LCCOMB_X2_Y20_N4 1 " "Info: 2: + IC(0.383 ns) + CELL(0.507 ns) = 0.890 ns; Loc. = LCCOMB_X2_Y20_N4; Fanout = 1; COMB Node = 'inst21~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.890 ns" { MyMemory:inst|MyDFF:inst13|Q inst21~0 } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { -432 744 808 -352 "inst21" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.512 ns) 2.183 ns inst21~4 3 COMB LCCOMB_X1_Y20_N2 1 " "Info: 3: + IC(0.781 ns) + CELL(0.512 ns) = 2.183 ns; Loc. = LCCOMB_X1_Y20_N2; Fanout = 1; COMB Node = 'inst21~4'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { inst21~0 inst21~4 } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { -432 744 808 -352 "inst21" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.298 ns) + CELL(0.178 ns) 2.659 ns inst21 4 COMB LCCOMB_X1_Y20_N16 2 " "Info: 4: + IC(0.298 ns) + CELL(0.178 ns) = 2.659 ns; Loc. = LCCOMB_X1_Y20_N16; Fanout = 2; COMB Node = 'inst21'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.476 ns" { inst21~4 inst21 } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { -432 744 808 -352 "inst21" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.803 ns) + CELL(2.840 ns) 11.302 ns red 5 PIN PIN_R20 0 " "Info: 5: + IC(5.803 ns) + CELL(2.840 ns) = 11.302 ns; Loc. = PIN_R20; Fanout = 0; PIN Node = 'red'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.643 ns" { inst21 red } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { -400 1072 1248 -384 "red" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.037 ns ( 35.72 % ) " "Info: Total cell delay = 4.037 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.265 ns ( 64.28 % ) " "Info: Total interconnect delay = 7.265 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "11.302 ns" { MyMemory:inst|MyDFF:inst13|Q inst21~0 inst21~4 inst21 red } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "11.302 ns" { MyMemory:inst|MyDFF:inst13|Q {} inst21~0 {} inst21~4 {} inst21 {} red {} } { 0.000ns 0.383ns 0.781ns 0.298ns 5.803ns } { 0.000ns 0.507ns 0.512ns 0.178ns 2.840ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { CLK CLK~clkctrl MyMemory:inst|MyDFF:inst13|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { CLK {} CLK~combout {} CLK~clkctrl {} MyMemory:inst|MyDFF:inst13|Q {} } { 0.000ns 0.000ns 0.238ns 0.964ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "11.302 ns" { MyMemory:inst|MyDFF:inst13|Q inst21~0 inst21~4 inst21 red } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "11.302 ns" { MyMemory:inst|MyDFF:inst13|Q {} inst21~0 {} inst21~4 {} inst21 {} red {} } { 0.000ns 0.383ns 0.781ns 0.298ns 5.803ns } { 0.000ns 0.507ns 0.512ns 0.178ns 2.840ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "MyMemory:inst26\|MyDFF:inst10\|Q SEL\[1\] CLK -0.260 ns register " "Info: th for register \"MyMemory:inst26\|MyDFF:inst10\|Q\" (data pin = \"SEL\[1\]\", clock pin = \"CLK\") is -0.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.809 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns CLK 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns CLK~clkctrl 2 COMB CLKCTRL_G11 24 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 24; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 432 -8 8 600 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.602 ns) 2.809 ns MyMemory:inst26\|MyDFF:inst10\|Q 3 REG LCFF_X1_Y20_N21 2 " "Info: 3: + IC(0.963 ns) + CELL(0.602 ns) = 2.809 ns; Loc. = LCFF_X1_Y20_N21; Fanout = 2; REG Node = 'MyMemory:inst26\|MyDFF:inst10\|Q'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { CLK~clkctrl MyMemory:inst26|MyDFF:inst10|Q } "NODE_NAME" } } { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 57.24 % ) " "Info: Total cell delay = 1.608 ns ( 57.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.201 ns ( 42.76 % ) " "Info: Total interconnect delay = 1.201 ns ( 42.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { CLK CLK~clkctrl MyMemory:inst26|MyDFF:inst10|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { CLK {} CLK~combout {} CLK~clkctrl {} MyMemory:inst26|MyDFF:inst10|Q {} } { 0.000ns 0.000ns 0.238ns 0.963ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.355 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SEL\[1\] 1 PIN PIN_M1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 4; PIN Node = 'SEL\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[1] } "NODE_NAME" } } { "Exp9.bdf" "" { Schematic "G:/Exp9/Exp9.bdf" { { 920 136 152 1088 "SEL\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.177 ns) 2.332 ns MyDecoder:inst8\|out\[0\]~7 2 COMB LCCOMB_X1_Y20_N14 6 " "Info: 2: + IC(1.129 ns) + CELL(0.177 ns) = 2.332 ns; Loc. = LCCOMB_X1_Y20_N14; Fanout = 6; COMB Node = 'MyDecoder:inst8\|out\[0\]~7'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.306 ns" { SEL[1] MyDecoder:inst8|out[0]~7 } "NODE_NAME" } } { "MyDecoder.v" "" { Text "G:/Exp9/MyDecoder.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.758 ns) 3.355 ns MyMemory:inst26\|MyDFF:inst10\|Q 3 REG LCFF_X1_Y20_N21 2 " "Info: 3: + IC(0.265 ns) + CELL(0.758 ns) = 3.355 ns; Loc. = LCFF_X1_Y20_N21; Fanout = 2; REG Node = 'MyMemory:inst26\|MyDFF:inst10\|Q'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.023 ns" { MyDecoder:inst8|out[0]~7 MyMemory:inst26|MyDFF:inst10|Q } "NODE_NAME" } } { "MyDFF.v" "" { Text "G:/Exp9/MyDFF.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.961 ns ( 58.45 % ) " "Info: Total cell delay = 1.961 ns ( 58.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.394 ns ( 41.55 % ) " "Info: Total interconnect delay = 1.394 ns ( 41.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.355 ns" { SEL[1] MyDecoder:inst8|out[0]~7 MyMemory:inst26|MyDFF:inst10|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.355 ns" { SEL[1] {} SEL[1]~combout {} MyDecoder:inst8|out[0]~7 {} MyMemory:inst26|MyDFF:inst10|Q {} } { 0.000ns 0.000ns 1.129ns 0.265ns } { 0.000ns 1.026ns 0.177ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { CLK CLK~clkctrl MyMemory:inst26|MyDFF:inst10|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { CLK {} CLK~combout {} CLK~clkctrl {} MyMemory:inst26|MyDFF:inst10|Q {} } { 0.000ns 0.000ns 0.238ns 0.963ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.355 ns" { SEL[1] MyDecoder:inst8|out[0]~7 MyMemory:inst26|MyDFF:inst10|Q } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.355 ns" { SEL[1] {} SEL[1]~combout {} MyDecoder:inst8|out[0]~7 {} MyMemory:inst26|MyDFF:inst10|Q {} } { 0.000ns 0.000ns 1.129ns 0.265ns } { 0.000ns 1.026ns 0.177ns 0.758ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Peak virtual memory: 162 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 15:20:21 2012 " "Info: Processing ended: Wed Nov 21 15:20:21 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 9 s " "Info: Quartus II Full Compilation was successful. 0 errors, 9 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
