Version 9.0 Build 132 02/25/2009 SJ Web Edition
11
980
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
sevenseg
# storage
db|seven.(1).cnf
db|seven.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sevenseg.v
8de203ee61cd35dde6772f27d10c8bd
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
sevenseg:inst
}
# macro_sequence

# end
# entity
seven
# storage
db|seven.(0).cnf
db|seven.(0).cnf
# case_insensitive
# source_file
seven.bdf
f2b42d8e1d111ad7f1243c4d5468a5
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# complete

