{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 21:46:38 2010 " "Info: Processing started: Tue Apr 20 21:46:38 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP2 -c SIMCOMP2 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP2 -c SIMCOMP2 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SIMCOMP2.v(28) " "Warning (10268): Verilog HDL information at SIMCOMP2.v(28): always construct contains both blocking and non-blocking assignments" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIMCOMP2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SIMCOMP2.v" { { "Info" "ISGN_ENTITY_NAME" "1 SIMCOMP2 " "Info: Found entity 1: SIMCOMP2" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "PC packed SIMCOMP2.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(6): data type declaration for \"PC\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "PC SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"PC\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R0 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R0\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R0 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R0\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R1 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R1\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R1 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R1\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R2 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R2\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R2 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R2\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R3 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R3\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R3 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R3\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "IR packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"IR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "IR SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"IR\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "MBR packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"MBR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "MBR SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"MBR\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "MAR packed SIMCOMP2.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(6): data type declaration for \"MAR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "MAR SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"MAR\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "SIMCOMP2 " "Info: Elaborating entity \"SIMCOMP2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 SIMCOMP2.v(38) " "Warning (10230): Verilog HDL assignment warning at SIMCOMP2.v(38): truncated value with size 32 to match size of target (12)" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "Memory~3 " "Warning: Inferred RAM node \"Memory~3\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "SIMCOMP2.v" "Memory~3" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 9 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0 -1}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "32 " "Info: Inferred 32 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" {  } { { "SIMCOMP2.v" "Mux0" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" {  } { { "SIMCOMP2.v" "Mux1" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" {  } { { "SIMCOMP2.v" "Mux2" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" {  } { { "SIMCOMP2.v" "Mux3" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux4\"" {  } { { "SIMCOMP2.v" "Mux4" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux5\"" {  } { { "SIMCOMP2.v" "Mux5" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux6\"" {  } { { "SIMCOMP2.v" "Mux6" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux7\"" {  } { { "SIMCOMP2.v" "Mux7" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux8\"" {  } { { "SIMCOMP2.v" "Mux8" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux9\"" {  } { { "SIMCOMP2.v" "Mux9" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux10\"" {  } { { "SIMCOMP2.v" "Mux10" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux11\"" {  } { { "SIMCOMP2.v" "Mux11" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux12\"" {  } { { "SIMCOMP2.v" "Mux12" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux13\"" {  } { { "SIMCOMP2.v" "Mux13" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux14 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux14\"" {  } { { "SIMCOMP2.v" "Mux14" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux15 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux15\"" {  } { { "SIMCOMP2.v" "Mux15" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux16 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux16\"" {  } { { "SIMCOMP2.v" "Mux16" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux17 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux17\"" {  } { { "SIMCOMP2.v" "Mux17" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux18 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux18\"" {  } { { "SIMCOMP2.v" "Mux18" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux19 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux19\"" {  } { { "SIMCOMP2.v" "Mux19" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux20 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux20\"" {  } { { "SIMCOMP2.v" "Mux20" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux21 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux21\"" {  } { { "SIMCOMP2.v" "Mux21" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux22 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux22\"" {  } { { "SIMCOMP2.v" "Mux22" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux23 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux23\"" {  } { { "SIMCOMP2.v" "Mux23" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux24 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux24\"" {  } { { "SIMCOMP2.v" "Mux24" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux25 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux25\"" {  } { { "SIMCOMP2.v" "Mux25" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux26 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux26\"" {  } { { "SIMCOMP2.v" "Mux26" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux27 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux27\"" {  } { { "SIMCOMP2.v" "Mux27" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux28 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux28\"" {  } { { "SIMCOMP2.v" "Mux28" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux29 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux29\"" {  } { { "SIMCOMP2.v" "Mux29" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux30 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux30\"" {  } { { "SIMCOMP2.v" "Mux30" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux31 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux31\"" {  } { { "SIMCOMP2.v" "Mux31" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:Memory_rtl_0 " "Info: Elaborated megafunction instantiation \"altsyncram:Memory_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altsyncram:Memory_rtl_0 " "Info: Instantiated megafunction \"altsyncram:Memory_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Info: Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 16 " "Info: Parameter \"WIDTH_A\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 6 " "Info: Parameter \"WIDTHAD_A\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 64 " "Info: Parameter \"NUMWORDS_A\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 16 " "Info: Parameter \"WIDTH_B\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 6 " "Info: Parameter \"WIDTHAD_B\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 64 " "Info: Parameter \"NUMWORDS_B\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Info: Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Info: Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Info: Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif " "Info: Parameter \"INIT_FILE\" = \"db/SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sin1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sin1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sin1 " "Info: Found entity 1: altsyncram_sin1" {  } { { "db/altsyncram_sin1.tdf" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/db/altsyncram_sin1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif " "Warning: Memory Initialization File or Hexadecimal (Intel-Format) File \"SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } { { "altsyncram.tdf" "" { Text "c:/altera/90/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "" 0 -1}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif " "Warning: Memory Initialization File or Hexadecimal (Intel-Format) File \"SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } { { "altsyncram.tdf" "" { Text "c:/altera/90/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux0 " "Info: Instantiated megafunction \"lpm_mux:Mux0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Info: Parameter \"LPM_SIZE\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Info: Parameter \"LPM_WIDTHS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_umc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_umc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_umc " "Info: Found entity 1: mux_umc" {  } { { "db/mux_umc.tdf" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/db/mux_umc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 12 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "197 " "Info: Peak virtual memory: 197 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 21:46:40 2010 " "Info: Processing ended: Tue Apr 20 21:46:40 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
