Analysis & Synthesis report for SIMCOMP
Tue Apr 20 19:35:29 2010
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |SIMCOMP|state
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Registers Added for RAM Pass-Through Logic
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated
 15. Parameter Settings for User Entity Instance: Top-level Entity: |SIMCOMP
 16. Parameter Settings for Inferred Entity Instance: altsyncram:Memory_rtl_0
 17. altsyncram Parameter Settings by Entity Instance
 18. Analysis & Synthesis Messages
 19. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Apr 20 19:35:29 2010   ;
; Quartus II Version                 ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name                      ; SIMCOMP                                 ;
; Top-level Entity Name              ; SIMCOMP                                 ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 118                                     ;
;     Total combinational functions  ; 78                                      ;
;     Dedicated logic registers      ; 100                                     ;
; Total registers                    ; 100                                     ;
; Total pins                         ; 73                                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 1,024                                   ;
; Embedded Multiplier 9-bit elements ; 0                                       ;
; Total PLLs                         ; 0                                       ;
+------------------------------------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                            ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option                                                         ; Setting            ; Default Value      ;
+----------------------------------------------------------------+--------------------+--------------------+
; Device                                                         ; EP2C20F484C7       ;                    ;
; Top-level entity name                                          ; SIMCOMP            ; SIMCOMP            ;
; Family name                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                        ; Off                ;                    ;
; Use smart compilation                                          ; Off                ; Off                ;
; Restructure Multiplexers                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                            ; Off                ; Off                ;
; Preserve fewer node names                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                      ; Off                ; Off                ;
; Verilog Version                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                       ; Auto               ; Auto               ;
; Safe State Machine                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                              ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                     ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                 ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                        ; On                 ; On                 ;
; Parallel Synthesis                                             ; Off                ; Off                ;
; DSP Block Balancing                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                             ; On                 ; On                 ;
; Power-Up Don't Care                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                 ; Off                ; Off                ;
; Optimization Technique                                         ; Balanced           ; Balanced           ;
; Carry Chain Length                                             ; 70                 ; 70                 ;
; Auto Carry Chains                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                          ; Off                ; Off                ;
; Auto ROM Replacement                                           ; On                 ; On                 ;
; Auto RAM Replacement                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                  ; On                 ; On                 ;
; Strict RAM Replacement                                         ; Off                ; Off                ;
; Allow Synchronous Control Signals                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                              ; Off                ; Off                ;
; Auto Resource Sharing                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                  ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing            ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives              ; Off                ; Off                ;
; Timing-Driven Synthesis                                        ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                             ; Off                ; Off                ;
; Synchronization Register Chain Length                          ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report       ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report      ; 100                ; 100                ;
; Clock MUX Protection                                           ; On                 ; On                 ;
; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                         ;
+------------------------------------------+-----------------+-------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path         ; Used in Netlist ; File Type                                             ; File Name with Absolute Path                                                                              ;
+------------------------------------------+-----------------+-------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
; SIMCOMP.v                                ; yes             ; User Verilog HDL File                                 ; E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/SIMCOMP.v                                ;
; altsyncram.tdf                           ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/altsyncram.tdf                                               ;
; stratix_ram_block.inc                    ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/stratix_ram_block.inc                                        ;
; lpm_mux.inc                              ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/lpm_mux.inc                                                  ;
; lpm_decode.inc                           ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/lpm_decode.inc                                               ;
; aglobal90.inc                            ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/aglobal90.inc                                                ;
; a_rdenreg.inc                            ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/a_rdenreg.inc                                                ;
; altrom.inc                               ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/altrom.inc                                                   ;
; altram.inc                               ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/altram.inc                                                   ;
; altdpram.inc                             ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/altdpram.inc                                                 ;
; altqpram.inc                             ; yes             ; Megafunction                                          ; c:/altera/90/quartus/libraries/megafunctions/altqpram.inc                                                 ;
; db/altsyncram_qcn1.tdf                   ; yes             ; Auto-Generated Megafunction                           ; E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/db/altsyncram_qcn1.tdf                   ;
; db/SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/db/SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif ;
+------------------------------------------+-----------------+-------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 118   ;
;                                             ;       ;
; Total combinational functions               ; 78    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 16    ;
;     -- 3 input functions                    ; 44    ;
;     -- <=2 input functions                  ; 18    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 53    ;
;     -- arithmetic mode                      ; 25    ;
;                                             ;       ;
; Total registers                             ; 100   ;
;     -- Dedicated logic registers            ; 100   ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 73    ;
; Total memory bits                           ; 1024  ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 116   ;
; Total fan-out                               ; 869   ;
; Average fan-out                             ; 3.25  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                 ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------+--------------+
; Compilation Hierarchy Node             ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                             ; Library Name ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------+--------------+
; |SIMCOMP                               ; 78 (78)           ; 100 (100)    ; 1024        ; 0            ; 0       ; 0         ; 73   ; 0            ; |SIMCOMP                                                        ; work         ;
;    |altsyncram:Memory_rtl_0|           ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |SIMCOMP|altsyncram:Memory_rtl_0                                ; work         ;
;       |altsyncram_qcn1:auto_generated| ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |SIMCOMP|altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated ; work         ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                          ;
+-------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------------------------------------------+
; Name                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                                      ;
+-------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------------------------------------------+
; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64           ; 16           ; 64           ; 16           ; 1024 ; db/SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif ;
+-------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------+
; State Machine - |SIMCOMP|state                                              ;
+------------+------------+------------+------------+------------+------------+
; Name       ; state.0011 ; state.0010 ; state.0001 ; state.0000 ; state.0100 ;
+------------+------------+------------+------------+------------+------------+
; state.0000 ; 0          ; 0          ; 0          ; 0          ; 0          ;
; state.0001 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; state.0010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; state.0011 ; 1          ; 0          ; 0          ; 1          ; 0          ;
; state.0100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
+------------+------------+------------+------------+------------+------------+


+-----------------------------------------------------------------+
; Registers Removed During Synthesis                              ;
+---------------------------------------+-------------------------+
; Register name                         ; Reason for Removal      ;
+---------------------------------------+-------------------------+
; Memory_5_bypass[2]                    ; Merged with MAR[0]~reg0 ;
; Memory_5_bypass[4]                    ; Merged with MAR[1]~reg0 ;
; Memory_5_bypass[6]                    ; Merged with MAR[2]~reg0 ;
; Memory_5_bypass[8]                    ; Merged with MAR[3]~reg0 ;
; Memory_5_bypass[10]                   ; Merged with MAR[4]~reg0 ;
; Memory_5_bypass[12]                   ; Merged with MAR[5]~reg0 ;
; state~21                              ; Lost fanout             ;
; state~22                              ; Lost fanout             ;
; state~24                              ; Lost fanout             ;
; Total Number of Removed Registers = 9 ;                         ;
+---------------------------------------+-------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 100   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 32    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 66    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; PC[1]~reg0                             ; 3       ;
; PC[3]~reg0                             ; 3       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+--------------------------------------------+
; Registers Added for RAM Pass-Through Logic ;
+---------------------+----------------------+
; Register Name       ; RAM Name             ;
+---------------------+----------------------+
; Memory_5_bypass[0]  ; Memory~5             ;
; Memory_5_bypass[1]  ; Memory~5             ;
; Memory_5_bypass[2]  ; Memory~5             ;
; Memory_5_bypass[3]  ; Memory~5             ;
; Memory_5_bypass[4]  ; Memory~5             ;
; Memory_5_bypass[5]  ; Memory~5             ;
; Memory_5_bypass[6]  ; Memory~5             ;
; Memory_5_bypass[7]  ; Memory~5             ;
; Memory_5_bypass[8]  ; Memory~5             ;
; Memory_5_bypass[9]  ; Memory~5             ;
; Memory_5_bypass[10] ; Memory~5             ;
; Memory_5_bypass[11] ; Memory~5             ;
; Memory_5_bypass[12] ; Memory~5             ;
; Memory_5_bypass[13] ; Memory~5             ;
; Memory_5_bypass[14] ; Memory~5             ;
; Memory_5_bypass[15] ; Memory~5             ;
; Memory_5_bypass[16] ; Memory~5             ;
; Memory_5_bypass[17] ; Memory~5             ;
; Memory_5_bypass[18] ; Memory~5             ;
; Memory_5_bypass[19] ; Memory~5             ;
; Memory_5_bypass[20] ; Memory~5             ;
; Memory_5_bypass[21] ; Memory~5             ;
; Memory_5_bypass[22] ; Memory~5             ;
; Memory_5_bypass[23] ; Memory~5             ;
; Memory_5_bypass[24] ; Memory~5             ;
; Memory_5_bypass[25] ; Memory~5             ;
; Memory_5_bypass[26] ; Memory~5             ;
; Memory_5_bypass[27] ; Memory~5             ;
; Memory_5_bypass[28] ; Memory~5             ;
+---------------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |SIMCOMP|AC[3]~reg0        ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |SIMCOMP|MAR[10]~reg0      ;
; 16:1               ; 16 bits   ; 160 LEs       ; 16 LEs               ; 144 LEs                ; Yes        ; |SIMCOMP|MBR[1]~reg0       ;
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |SIMCOMP|Selector32        ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |SIMCOMP|state~14          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------------------------------------------------------+
; Source assignments for altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated ;
+---------------------------------+--------------------+------+-----------------+
; Assignment                      ; Value              ; From ; To              ;
+---------------------------------+--------------------+------+-----------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -               ;
+---------------------------------+--------------------+------+-----------------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |SIMCOMP ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; load           ; 0011  ; Unsigned Binary                                ;
; store          ; 1011  ; Unsigned Binary                                ;
; add            ; 0111  ; Unsigned Binary                                ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altsyncram:Memory_rtl_0                       ;
+------------------------------------+------------------------------------------+----------------+
; Parameter Name                     ; Value                                    ; Type           ;
+------------------------------------+------------------------------------------+----------------+
; BYTE_SIZE_BLOCK                    ; 8                                        ; Untyped        ;
; AUTO_CARRY_CHAINS                  ; ON                                       ; AUTO_CARRY     ;
; IGNORE_CARRY_BUFFERS               ; OFF                                      ; IGNORE_CARRY   ;
; AUTO_CASCADE_CHAINS                ; ON                                       ; AUTO_CASCADE   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                      ; IGNORE_CASCADE ;
; WIDTH_BYTEENA                      ; 1                                        ; Untyped        ;
; OPERATION_MODE                     ; DUAL_PORT                                ; Untyped        ;
; WIDTH_A                            ; 16                                       ; Untyped        ;
; WIDTHAD_A                          ; 6                                        ; Untyped        ;
; NUMWORDS_A                         ; 64                                       ; Untyped        ;
; OUTDATA_REG_A                      ; UNREGISTERED                             ; Untyped        ;
; ADDRESS_ACLR_A                     ; NONE                                     ; Untyped        ;
; OUTDATA_ACLR_A                     ; NONE                                     ; Untyped        ;
; WRCONTROL_ACLR_A                   ; NONE                                     ; Untyped        ;
; INDATA_ACLR_A                      ; NONE                                     ; Untyped        ;
; BYTEENA_ACLR_A                     ; NONE                                     ; Untyped        ;
; WIDTH_B                            ; 16                                       ; Untyped        ;
; WIDTHAD_B                          ; 6                                        ; Untyped        ;
; NUMWORDS_B                         ; 64                                       ; Untyped        ;
; INDATA_REG_B                       ; CLOCK1                                   ; Untyped        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                   ; Untyped        ;
; RDCONTROL_REG_B                    ; CLOCK1                                   ; Untyped        ;
; ADDRESS_REG_B                      ; CLOCK0                                   ; Untyped        ;
; OUTDATA_REG_B                      ; UNREGISTERED                             ; Untyped        ;
; BYTEENA_REG_B                      ; CLOCK1                                   ; Untyped        ;
; INDATA_ACLR_B                      ; NONE                                     ; Untyped        ;
; WRCONTROL_ACLR_B                   ; NONE                                     ; Untyped        ;
; ADDRESS_ACLR_B                     ; NONE                                     ; Untyped        ;
; OUTDATA_ACLR_B                     ; NONE                                     ; Untyped        ;
; RDCONTROL_ACLR_B                   ; NONE                                     ; Untyped        ;
; BYTEENA_ACLR_B                     ; NONE                                     ; Untyped        ;
; WIDTH_BYTEENA_A                    ; 1                                        ; Untyped        ;
; WIDTH_BYTEENA_B                    ; 1                                        ; Untyped        ;
; RAM_BLOCK_TYPE                     ; AUTO                                     ; Untyped        ;
; BYTE_SIZE                          ; 8                                        ; Untyped        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                 ; Untyped        ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                     ; Untyped        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                     ; Untyped        ;
; INIT_FILE                          ; db/SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif ; Untyped        ;
; INIT_FILE_LAYOUT                   ; PORT_A                                   ; Untyped        ;
; MAXIMUM_DEPTH                      ; 0                                        ; Untyped        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                                   ; Untyped        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                   ; Untyped        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                                   ; Untyped        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                   ; Untyped        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                          ; Untyped        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                          ; Untyped        ;
; ENABLE_ECC                         ; FALSE                                    ; Untyped        ;
; DEVICE_FAMILY                      ; Cyclone II                               ; Untyped        ;
; CBXI_PARAMETER                     ; altsyncram_qcn1                          ; Untyped        ;
+------------------------------------+------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                    ;
+-------------------------------------------+-------------------------+
; Name                                      ; Value                   ;
+-------------------------------------------+-------------------------+
; Number of entity instances                ; 1                       ;
; Entity Instance                           ; altsyncram:Memory_rtl_0 ;
;     -- OPERATION_MODE                     ; DUAL_PORT               ;
;     -- WIDTH_A                            ; 16                      ;
;     -- NUMWORDS_A                         ; 64                      ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED            ;
;     -- WIDTH_B                            ; 16                      ;
;     -- NUMWORDS_B                         ; 64                      ;
;     -- ADDRESS_REG_B                      ; CLOCK0                  ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED            ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                    ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                ;
+-------------------------------------------+-------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Tue Apr 20 19:35:24 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP -c SIMCOMP
Info: Found 1 design units, including 1 entities, in source file SIMCOMP.v
    Info: Found entity 1: SIMCOMP
Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP.v(5): data type declaration for "PC" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at SIMCOMP.v(3): "PC" is declared here
Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP.v(4): data type declaration for "AC" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at SIMCOMP.v(3): "AC" is declared here
Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP.v(4): data type declaration for "IP" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at SIMCOMP.v(3): "IP" is declared here
Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP.v(4): data type declaration for "MBR" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at SIMCOMP.v(3): "MBR" is declared here
Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP.v(5): data type declaration for "MAR" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at SIMCOMP.v(3): "MAR" is declared here
Info: Elaborating entity "SIMCOMP" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at SIMCOMP.v(34): truncated value with size 32 to match size of target (12)
Warning: Inferred RAM node "Memory~5" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction from the following design logic: "Memory~5" 
        Info: Parameter OPERATION_MODE set to DUAL_PORT
        Info: Parameter WIDTH_A set to 16
        Info: Parameter WIDTHAD_A set to 6
        Info: Parameter NUMWORDS_A set to 64
        Info: Parameter WIDTH_B set to 16
        Info: Parameter WIDTHAD_B set to 6
        Info: Parameter NUMWORDS_B set to 64
        Info: Parameter ADDRESS_ACLR_A set to NONE
        Info: Parameter OUTDATA_REG_B set to UNREGISTERED
        Info: Parameter ADDRESS_ACLR_B set to NONE
        Info: Parameter OUTDATA_ACLR_B set to NONE
        Info: Parameter ADDRESS_REG_B set to CLOCK0
        Info: Parameter INDATA_ACLR_A set to NONE
        Info: Parameter WRCONTROL_ACLR_A set to NONE
        Info: Parameter RAM_BLOCK_TYPE set to AUTO
        Info: Parameter INIT_FILE set to db/SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif
        Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info: Elaborated megafunction instantiation "altsyncram:Memory_rtl_0"
Info: Instantiated megafunction "altsyncram:Memory_rtl_0" with the following parameter:
    Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info: Parameter "WIDTH_A" = "16"
    Info: Parameter "WIDTHAD_A" = "6"
    Info: Parameter "NUMWORDS_A" = "64"
    Info: Parameter "WIDTH_B" = "16"
    Info: Parameter "WIDTHAD_B" = "6"
    Info: Parameter "NUMWORDS_B" = "64"
    Info: Parameter "ADDRESS_ACLR_A" = "NONE"
    Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info: Parameter "ADDRESS_ACLR_B" = "NONE"
    Info: Parameter "OUTDATA_ACLR_B" = "NONE"
    Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
    Info: Parameter "INDATA_ACLR_A" = "NONE"
    Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info: Parameter "RAM_BLOCK_TYPE" = "AUTO"
    Info: Parameter "INIT_FILE" = "db/SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif"
    Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qcn1.tdf
    Info: Found entity 1: altsyncram_qcn1
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File "SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif" contains "don't care" values -- overwriting them with 0s
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File "SIMCOMP.ram0_SIMCOMP_a9406e56.hdl.mif" contains "don't care" values -- overwriting them with 0s
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "state~21" lost all its fanouts during netlist optimizations.
    Info: Register "state~22" lost all its fanouts during netlist optimizations.
    Info: Register "state~24" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/SIMCOMP.map.smsg
Info: Implemented 230 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 72 output pins
    Info: Implemented 141 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 198 megabytes
    Info: Processing ended: Tue Apr 20 19:35:29 2010
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/SIMCOMP.map.smsg.


