module counter (clk, reset, count);
input clk, reset;
wire clk, reset;
output [3:0] count;
reg [3:0] count;
reg [3:0]c; //counter
initial c=4'b0000;

always @(posedge clk) begin

if(reset==1)begin
 count=4'b0000;
 c=4'b0000;
 end
else if(c<=4'b1111) begin
 count= count+1;
 c=c+1;
 end
if (c==4'b0000) begin
  count=4'b0000;
  c=4'b0000;
  end
  
end
endmodule 




module freq_div(freq1,rst,freq2);
input freq1, rst;
output freq2;
wire freq1,rst;
reg freq2;
reg [2:0] counter;
always @ (posedge freq1 or negedge rst)
begin
if(rst==0)
 begin
  counter=0;
  freq2=0;
 end
else
 begin
  if(counter==0)
   begin
    counter=4;
    freq2=0;
   end
  else
   begin
    counter=counter-1;
    freq2=1;
   end
 end
end 
endmodule 



module sevenseg(in,out);
input [3:0] in;
output [6:0] out;
wire [3:0] in;
reg [6:0] out;
always @ (in)
begin
case(in)
0 : out= 7'b0111111 ;
1 : out= 7'b0000110 ;
2 : out= 7'b1011011 ;
3 : out= 7'b1001111 ;
4 : out= 7'b1100110 ;
5 : out= 7'b1101101 ;
6 : out= 7'b1111101 ;
7 : out= 7'b0000111 ;
8 : out= 7'b1111111 ;
9 : out= 7'b1101111 ;
10: out= 7'b1110111 ;
11: out= 7'b1111100 ;
12: out= 7'b0111001 ;
13: out= 7'b1011110 ;
14: out= 7'b1111001 ;
15: out= 7'b1110001 ;
endcase
end
endmodule
