module freq_div(freq1,rst,freq2);
input freq1, rst;
output freq2;
wire freq1,rst;
reg freq2;
reg [25:0] counter;
always @ (posedge freq1 or negedge rst)
begin
 
if(rst==0)
 begin
  counter=0;
  freq2=0;
 end
else
 begin
  if(counter==0)
   begin
    counter=13000000;
    freq2=0;
   end
  else
   begin
    counter=counter-1;
    freq2=1;
   end
 end
end 
endmodule 