Simulator report for SecuritySystem
Wed Mar 31 13:28:30 2010
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Coverage Summary
  6. Complete 1/0-Value Coverage
  7. Missing 1-Value Coverage
  8. Missing 0-Value Coverage
  9. Simulator INI Usage
 10. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 70.0 ns      ;
; Simulation Netlist Size     ; 136 nodes    ;
; Simulation Coverage         ;      20.15 % ;
; Total Number of Transitions ; 158          ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone II   ;
+-----------------------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                      ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option                                                                                     ; Setting    ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode                                                                            ; Functional ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Simulation results format                                                                  ; CVWF       ;               ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      20.15 % ;
; Total nodes checked                                 ; 136          ;
; Total output ports checked                          ; 134          ;
; Total output ports with complete 1/0-value coverage ; 27           ;
; Total output ports with no 1/0-value coverage       ; 98           ;
; Total output ports with no 1-value coverage         ; 99           ;
; Total output ports with no 0-value coverage         ; 106          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                          ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; Node Name                                       ; Output Port Name                                ; Output Port Type ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; |SecuritySystem|CLK                             ; |SecuritySystem|CLK                             ; out              ;
; |SecuritySystem|en                              ; |SecuritySystem|en                              ; out              ;
; |SecuritySystem|Sel[1]                          ; |SecuritySystem|Sel[1]                          ; out              ;
; |SecuritySystem|Sel[0]                          ; |SecuritySystem|Sel[0]                          ; out              ;
; |SecuritySystem|I2                              ; |SecuritySystem|I2                              ; out              ;
; |SecuritySystem|I3                              ; |SecuritySystem|I3                              ; out              ;
; |SecuritySystem|I4                              ; |SecuritySystem|I4                              ; out              ;
; |SecuritySystem|I6                              ; |SecuritySystem|I6                              ; out              ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst8|out  ; |SecuritySystem|MyMemory:inst3|MyMux:inst8|out  ; out              ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst11|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst11|out ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~0        ; |SecuritySystem|MyEncoder:inst5|en_out~0        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~1        ; |SecuritySystem|MyEncoder:inst5|en_out~1        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~3        ; |SecuritySystem|MyEncoder:inst5|en_out~3        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~4        ; |SecuritySystem|MyEncoder:inst5|en_out~4        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out[1]       ; |SecuritySystem|MyEncoder:inst5|en_out[1]       ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out[0]       ; |SecuritySystem|MyEncoder:inst5|en_out[0]       ; out              ;
; |SecuritySystem|sevenseg:inst6|WideOr2          ; |SecuritySystem|sevenseg:inst6|WideOr2          ; out0             ;
; |SecuritySystem|MYDecoder:inst4|out[3]          ; |SecuritySystem|MYDecoder:inst4|out[3]          ; out              ;
; |SecuritySystem|MYDecoder:inst4|out[1]          ; |SecuritySystem|MYDecoder:inst4|out[1]          ; out              ;
; |SecuritySystem|MYDecoder:inst4|out[0]          ; |SecuritySystem|MYDecoder:inst4|out[0]          ; out              ;
; |SecuritySystem|MyMemory:inst|MyMux:inst11|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst11|out  ; out              ;
; |SecuritySystem|sevenseg:inst6|Decoder0~5       ; |SecuritySystem|sevenseg:inst6|Decoder0~5       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~6       ; |SecuritySystem|sevenseg:inst6|Decoder0~6       ; out0             ;
; |SecuritySystem|MYDecoder:inst4|Decoder0~0      ; |SecuritySystem|MYDecoder:inst4|Decoder0~0      ; out0             ;
; |SecuritySystem|MYDecoder:inst4|Decoder0~1      ; |SecuritySystem|MYDecoder:inst4|Decoder0~1      ; out0             ;
; |SecuritySystem|MYDecoder:inst4|Decoder0~2      ; |SecuritySystem|MYDecoder:inst4|Decoder0~2      ; out0             ;
; |SecuritySystem|MYDecoder:inst4|Decoder0~3      ; |SecuritySystem|MYDecoder:inst4|Decoder0~3      ; out0             ;
+-------------------------------------------------+-------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                             ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; Node Name                                       ; Output Port Name                                ; Output Port Type ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; |SecuritySystem|red                             ; |SecuritySystem|red                             ; pin_out          ;
; |SecuritySystem|inst21                          ; |SecuritySystem|inst21                          ; out0             ;
; |SecuritySystem|I1                              ; |SecuritySystem|I1                              ; out              ;
; |SecuritySystem|I5                              ; |SecuritySystem|I5                              ; out              ;
; |SecuritySystem|green                           ; |SecuritySystem|green                           ; pin_out          ;
; |SecuritySystem|Dis1[6]                         ; |SecuritySystem|Dis1[6]                         ; pin_out          ;
; |SecuritySystem|Dis1[5]                         ; |SecuritySystem|Dis1[5]                         ; pin_out          ;
; |SecuritySystem|Dis1[3]                         ; |SecuritySystem|Dis1[3]                         ; pin_out          ;
; |SecuritySystem|Dis1[2]                         ; |SecuritySystem|Dis1[2]                         ; pin_out          ;
; |SecuritySystem|Dis1[0]                         ; |SecuritySystem|Dis1[0]                         ; pin_out          ;
; |SecuritySystem|Dis2[6]                         ; |SecuritySystem|Dis2[6]                         ; pin_out          ;
; |SecuritySystem|Dis2[5]                         ; |SecuritySystem|Dis2[5]                         ; pin_out          ;
; |SecuritySystem|Dis2[4]                         ; |SecuritySystem|Dis2[4]                         ; pin_out          ;
; |SecuritySystem|Dis2[3]                         ; |SecuritySystem|Dis2[3]                         ; pin_out          ;
; |SecuritySystem|Dis2[2]                         ; |SecuritySystem|Dis2[2]                         ; pin_out          ;
; |SecuritySystem|Dis2[0]                         ; |SecuritySystem|Dis2[0]                         ; pin_out          ;
; |SecuritySystem|Dis3[6]                         ; |SecuritySystem|Dis3[6]                         ; pin_out          ;
; |SecuritySystem|Dis3[5]                         ; |SecuritySystem|Dis3[5]                         ; pin_out          ;
; |SecuritySystem|Dis3[4]                         ; |SecuritySystem|Dis3[4]                         ; pin_out          ;
; |SecuritySystem|Dis3[3]                         ; |SecuritySystem|Dis3[3]                         ; pin_out          ;
; |SecuritySystem|Dis3[2]                         ; |SecuritySystem|Dis3[2]                         ; pin_out          ;
; |SecuritySystem|Dis3[1]                         ; |SecuritySystem|Dis3[1]                         ; pin_out          ;
; |SecuritySystem|Dis3[0]                         ; |SecuritySystem|Dis3[0]                         ; pin_out          ;
; |SecuritySystem|Dis4[6]                         ; |SecuritySystem|Dis4[6]                         ; pin_out          ;
; |SecuritySystem|Dis4[5]                         ; |SecuritySystem|Dis4[5]                         ; pin_out          ;
; |SecuritySystem|Dis4[4]                         ; |SecuritySystem|Dis4[4]                         ; pin_out          ;
; |SecuritySystem|Dis4[3]                         ; |SecuritySystem|Dis4[3]                         ; pin_out          ;
; |SecuritySystem|Dis4[2]                         ; |SecuritySystem|Dis4[2]                         ; pin_out          ;
; |SecuritySystem|Dis4[1]                         ; |SecuritySystem|Dis4[1]                         ; pin_out          ;
; |SecuritySystem|Dis4[0]                         ; |SecuritySystem|Dis4[0]                         ; pin_out          ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst13|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst13|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst6|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst6|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst12|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst12|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst5|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst5|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst11|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst11|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst4|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst4|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst10|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst10|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst3|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst3|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst9|out  ; |SecuritySystem|MyMemory:inst3|MyMux:inst9|out  ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst2|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst2|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst1|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst1|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst7|out  ; |SecuritySystem|MyMemory:inst3|MyMux:inst7|out  ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst|Q     ; |SecuritySystem|MyMemory:inst3|MyDFF:inst|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst13|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst13|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst6|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst6|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst12|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst12|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst5|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst5|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst11|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst11|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst4|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst4|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst10|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst10|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst3|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst3|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst9|out  ; |SecuritySystem|MyMemory:inst2|MyMux:inst9|out  ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst2|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst2|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst8|out  ; |SecuritySystem|MyMemory:inst2|MyMux:inst8|out  ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst1|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst1|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst7|out  ; |SecuritySystem|MyMemory:inst2|MyMux:inst7|out  ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst|Q     ; |SecuritySystem|MyMemory:inst2|MyDFF:inst|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst13|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst13|out ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst6|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst6|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst12|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst12|out ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst5|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst5|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst4|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst4|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst10|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst10|out ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst3|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst3|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst9|out  ; |SecuritySystem|MyMemory:inst1|MyMux:inst9|out  ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst2|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst2|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst7|out  ; |SecuritySystem|MyMemory:inst1|MyMux:inst7|out  ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst|Q     ; |SecuritySystem|MyMemory:inst1|MyDFF:inst|Q     ; regout           ;
; |SecuritySystem|MyEncoder:inst5|en_out~2        ; |SecuritySystem|MyEncoder:inst5|en_out~2        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~5        ; |SecuritySystem|MyEncoder:inst5|en_out~5        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~6        ; |SecuritySystem|MyEncoder:inst5|en_out~6        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~7        ; |SecuritySystem|MyEncoder:inst5|en_out~7        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out[2]       ; |SecuritySystem|MyEncoder:inst5|en_out[2]       ; out              ;
; |SecuritySystem|sevenseg:inst6|WideOr0          ; |SecuritySystem|sevenseg:inst6|WideOr0          ; out0             ;
; |SecuritySystem|sevenseg:inst6|WideOr1          ; |SecuritySystem|sevenseg:inst6|WideOr1          ; out0             ;
; |SecuritySystem|sevenseg:inst6|WideOr3          ; |SecuritySystem|sevenseg:inst6|WideOr3          ; out0             ;
; |SecuritySystem|sevenseg:inst6|out[1]           ; |SecuritySystem|sevenseg:inst6|out[1]           ; out0             ;
; |SecuritySystem|sevenseg:inst6|out[0]           ; |SecuritySystem|sevenseg:inst6|out[0]           ; out0             ;
; |SecuritySystem|MYDecoder:inst4|out[2]          ; |SecuritySystem|MYDecoder:inst4|out[2]          ; out              ;
; |SecuritySystem|MyMemory:inst|MyMux:inst13|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst13|out  ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst6|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst6|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst12|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst12|out  ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst5|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst5|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst10|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst10|out  ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst3|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst3|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst9|out   ; |SecuritySystem|MyMemory:inst|MyMux:inst9|out   ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst2|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst2|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst8|out   ; |SecuritySystem|MyMemory:inst|MyMux:inst8|out   ; out              ;
; |SecuritySystem|MyMemory:inst|MyMux:inst7|out   ; |SecuritySystem|MyMemory:inst|MyMux:inst7|out   ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst|Q      ; |SecuritySystem|MyMemory:inst|MyDFF:inst|Q      ; regout           ;
; |SecuritySystem|sevenseg:inst6|Decoder0~0       ; |SecuritySystem|sevenseg:inst6|Decoder0~0       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~1       ; |SecuritySystem|sevenseg:inst6|Decoder0~1       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~2       ; |SecuritySystem|sevenseg:inst6|Decoder0~2       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~3       ; |SecuritySystem|sevenseg:inst6|Decoder0~3       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~4       ; |SecuritySystem|sevenseg:inst6|Decoder0~4       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~7       ; |SecuritySystem|sevenseg:inst6|Decoder0~7       ; out0             ;
; |SecuritySystem|MyComp:inst20|Equal0~0          ; |SecuritySystem|MyComp:inst20|Equal0~0          ; out0             ;
; |SecuritySystem|MyComp:inst19|Equal0~0          ; |SecuritySystem|MyComp:inst19|Equal0~0          ; out0             ;
; |SecuritySystem|MyComp:inst18|Equal0~0          ; |SecuritySystem|MyComp:inst18|Equal0~0          ; out0             ;
+-------------------------------------------------+-------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                             ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; Node Name                                       ; Output Port Name                                ; Output Port Type ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; |SecuritySystem|red                             ; |SecuritySystem|red                             ; pin_out          ;
; |SecuritySystem|inst21                          ; |SecuritySystem|inst21                          ; out0             ;
; |SecuritySystem|I5                              ; |SecuritySystem|I5                              ; out              ;
; |SecuritySystem|green                           ; |SecuritySystem|green                           ; pin_out          ;
; |SecuritySystem|Dis1[6]                         ; |SecuritySystem|Dis1[6]                         ; pin_out          ;
; |SecuritySystem|Dis1[5]                         ; |SecuritySystem|Dis1[5]                         ; pin_out          ;
; |SecuritySystem|Dis1[4]                         ; |SecuritySystem|Dis1[4]                         ; pin_out          ;
; |SecuritySystem|Dis1[3]                         ; |SecuritySystem|Dis1[3]                         ; pin_out          ;
; |SecuritySystem|Dis1[2]                         ; |SecuritySystem|Dis1[2]                         ; pin_out          ;
; |SecuritySystem|Dis1[1]                         ; |SecuritySystem|Dis1[1]                         ; pin_out          ;
; |SecuritySystem|Dis1[0]                         ; |SecuritySystem|Dis1[0]                         ; pin_out          ;
; |SecuritySystem|Dis2[6]                         ; |SecuritySystem|Dis2[6]                         ; pin_out          ;
; |SecuritySystem|Dis2[5]                         ; |SecuritySystem|Dis2[5]                         ; pin_out          ;
; |SecuritySystem|Dis2[4]                         ; |SecuritySystem|Dis2[4]                         ; pin_out          ;
; |SecuritySystem|Dis2[3]                         ; |SecuritySystem|Dis2[3]                         ; pin_out          ;
; |SecuritySystem|Dis2[2]                         ; |SecuritySystem|Dis2[2]                         ; pin_out          ;
; |SecuritySystem|Dis2[1]                         ; |SecuritySystem|Dis2[1]                         ; pin_out          ;
; |SecuritySystem|Dis2[0]                         ; |SecuritySystem|Dis2[0]                         ; pin_out          ;
; |SecuritySystem|Dis3[6]                         ; |SecuritySystem|Dis3[6]                         ; pin_out          ;
; |SecuritySystem|Dis3[5]                         ; |SecuritySystem|Dis3[5]                         ; pin_out          ;
; |SecuritySystem|Dis3[4]                         ; |SecuritySystem|Dis3[4]                         ; pin_out          ;
; |SecuritySystem|Dis3[3]                         ; |SecuritySystem|Dis3[3]                         ; pin_out          ;
; |SecuritySystem|Dis3[2]                         ; |SecuritySystem|Dis3[2]                         ; pin_out          ;
; |SecuritySystem|Dis3[1]                         ; |SecuritySystem|Dis3[1]                         ; pin_out          ;
; |SecuritySystem|Dis3[0]                         ; |SecuritySystem|Dis3[0]                         ; pin_out          ;
; |SecuritySystem|Dis4[6]                         ; |SecuritySystem|Dis4[6]                         ; pin_out          ;
; |SecuritySystem|Dis4[5]                         ; |SecuritySystem|Dis4[5]                         ; pin_out          ;
; |SecuritySystem|Dis4[4]                         ; |SecuritySystem|Dis4[4]                         ; pin_out          ;
; |SecuritySystem|Dis4[3]                         ; |SecuritySystem|Dis4[3]                         ; pin_out          ;
; |SecuritySystem|Dis4[2]                         ; |SecuritySystem|Dis4[2]                         ; pin_out          ;
; |SecuritySystem|Dis4[1]                         ; |SecuritySystem|Dis4[1]                         ; pin_out          ;
; |SecuritySystem|Dis4[0]                         ; |SecuritySystem|Dis4[0]                         ; pin_out          ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst13|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst13|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst6|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst6|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst12|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst12|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst5|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst5|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst11|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst11|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst4|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst4|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst10|out ; |SecuritySystem|MyMemory:inst3|MyMux:inst10|out ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst3|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst3|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst9|out  ; |SecuritySystem|MyMemory:inst3|MyMux:inst9|out  ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst2|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst2|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst1|Q    ; |SecuritySystem|MyMemory:inst3|MyDFF:inst1|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst3|MyMux:inst7|out  ; |SecuritySystem|MyMemory:inst3|MyMux:inst7|out  ; out              ;
; |SecuritySystem|MyMemory:inst3|MyDFF:inst|Q     ; |SecuritySystem|MyMemory:inst3|MyDFF:inst|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst13|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst13|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst6|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst6|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst12|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst12|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst5|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst5|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst11|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst11|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst4|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst4|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst10|out ; |SecuritySystem|MyMemory:inst2|MyMux:inst10|out ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst3|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst3|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst9|out  ; |SecuritySystem|MyMemory:inst2|MyMux:inst9|out  ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst2|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst2|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst8|out  ; |SecuritySystem|MyMemory:inst2|MyMux:inst8|out  ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst1|Q    ; |SecuritySystem|MyMemory:inst2|MyDFF:inst1|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst2|MyMux:inst7|out  ; |SecuritySystem|MyMemory:inst2|MyMux:inst7|out  ; out              ;
; |SecuritySystem|MyMemory:inst2|MyDFF:inst|Q     ; |SecuritySystem|MyMemory:inst2|MyDFF:inst|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst13|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst13|out ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst6|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst6|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst12|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst12|out ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst5|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst5|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst4|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst4|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst10|out ; |SecuritySystem|MyMemory:inst1|MyMux:inst10|out ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst3|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst3|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst9|out  ; |SecuritySystem|MyMemory:inst1|MyMux:inst9|out  ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst2|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst2|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst8|out  ; |SecuritySystem|MyMemory:inst1|MyMux:inst8|out  ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst1|Q    ; |SecuritySystem|MyMemory:inst1|MyDFF:inst1|Q    ; regout           ;
; |SecuritySystem|MyMemory:inst1|MyMux:inst7|out  ; |SecuritySystem|MyMemory:inst1|MyMux:inst7|out  ; out              ;
; |SecuritySystem|MyMemory:inst1|MyDFF:inst|Q     ; |SecuritySystem|MyMemory:inst1|MyDFF:inst|Q     ; regout           ;
; |SecuritySystem|MyEncoder:inst5|en_out~2        ; |SecuritySystem|MyEncoder:inst5|en_out~2        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~5        ; |SecuritySystem|MyEncoder:inst5|en_out~5        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~6        ; |SecuritySystem|MyEncoder:inst5|en_out~6        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out~7        ; |SecuritySystem|MyEncoder:inst5|en_out~7        ; out              ;
; |SecuritySystem|MyEncoder:inst5|en_out[2]       ; |SecuritySystem|MyEncoder:inst5|en_out[2]       ; out              ;
; |SecuritySystem|sevenseg:inst6|WideOr0          ; |SecuritySystem|sevenseg:inst6|WideOr0          ; out0             ;
; |SecuritySystem|sevenseg:inst6|WideOr1          ; |SecuritySystem|sevenseg:inst6|WideOr1          ; out0             ;
; |SecuritySystem|sevenseg:inst6|WideOr3          ; |SecuritySystem|sevenseg:inst6|WideOr3          ; out0             ;
; |SecuritySystem|sevenseg:inst6|out[1]           ; |SecuritySystem|sevenseg:inst6|out[1]           ; out0             ;
; |SecuritySystem|sevenseg:inst6|out[0]           ; |SecuritySystem|sevenseg:inst6|out[0]           ; out0             ;
; |SecuritySystem|MYDecoder:inst4|out[2]          ; |SecuritySystem|MYDecoder:inst4|out[2]          ; out              ;
; |SecuritySystem|MyMemory:inst|MyMux:inst13|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst13|out  ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst6|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst6|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst12|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst12|out  ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst5|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst5|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst4|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst4|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst10|out  ; |SecuritySystem|MyMemory:inst|MyMux:inst10|out  ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst3|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst3|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst9|out   ; |SecuritySystem|MyMemory:inst|MyMux:inst9|out   ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst2|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst2|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst8|out   ; |SecuritySystem|MyMemory:inst|MyMux:inst8|out   ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst1|Q     ; |SecuritySystem|MyMemory:inst|MyDFF:inst1|Q     ; regout           ;
; |SecuritySystem|MyMemory:inst|MyMux:inst7|out   ; |SecuritySystem|MyMemory:inst|MyMux:inst7|out   ; out              ;
; |SecuritySystem|MyMemory:inst|MyDFF:inst|Q      ; |SecuritySystem|MyMemory:inst|MyDFF:inst|Q      ; regout           ;
; |SecuritySystem|sevenseg:inst6|Decoder0~0       ; |SecuritySystem|sevenseg:inst6|Decoder0~0       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~1       ; |SecuritySystem|sevenseg:inst6|Decoder0~1       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~2       ; |SecuritySystem|sevenseg:inst6|Decoder0~2       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~3       ; |SecuritySystem|sevenseg:inst6|Decoder0~3       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~4       ; |SecuritySystem|sevenseg:inst6|Decoder0~4       ; out0             ;
; |SecuritySystem|sevenseg:inst6|Decoder0~7       ; |SecuritySystem|sevenseg:inst6|Decoder0~7       ; out0             ;
; |SecuritySystem|MyComp:inst20|Equal0~0          ; |SecuritySystem|MyComp:inst20|Equal0~0          ; out0             ;
; |SecuritySystem|MyComp:inst19|Equal0~0          ; |SecuritySystem|MyComp:inst19|Equal0~0          ; out0             ;
; |SecuritySystem|MyComp:inst18|Equal0~0          ; |SecuritySystem|MyComp:inst18|Equal0~0          ; out0             ;
; |SecuritySystem|MyComp:inst17|Equal0~0          ; |SecuritySystem|MyComp:inst17|Equal0~0          ; out0             ;
+-------------------------------------------------+-------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Wed Mar 31 13:28:28 2010
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off SecuritySystem -c SecuritySystem
Info: Using vector source file "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/Security System/SecuritySystem.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      20.15 %
Info: Number of transitions in simulation is 158
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 135 megabytes
    Info: Processing ended: Wed Mar 31 13:28:31 2010
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03


