|all
out[0] <= sevenseg:inst2.out[0]
out[1] <= sevenseg:inst2.out[1]
out[2] <= sevenseg:inst2.out[2]
out[3] <= sevenseg:inst2.out[3]
out[4] <= sevenseg:inst2.out[4]
out[5] <= sevenseg:inst2.out[5]
out[6] <= sevenseg:inst2.out[6]
clock => freq_div:inst.freq1
reset => freq_div:inst.rst
reset => counter:inst1.reset


|all|sevenseg:inst2
in[0] => Decoder0.IN3
in[1] => Decoder0.IN2
in[2] => Decoder0.IN1
in[3] => Decoder0.IN0
out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE


|all|counter:inst1
clk => count[3]~reg0.CLK
clk => count[2]~reg0.CLK
clk => count[1]~reg0.CLK
clk => count[0]~reg0.CLK
clk => c[3].CLK
clk => c[2].CLK
clk => c[1].CLK
clk => c[0].CLK
reset => c~7.OUTPUTSELECT
reset => c~6.OUTPUTSELECT
reset => c~5.OUTPUTSELECT
reset => c~4.OUTPUTSELECT
reset => count~7.OUTPUTSELECT
reset => count~6.OUTPUTSELECT
reset => count~5.OUTPUTSELECT
reset => count~4.OUTPUTSELECT
count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all|freq_div:inst
freq1 => counter[100].CLK
freq1 => counter[99].CLK
freq1 => counter[98].CLK
freq1 => counter[97].CLK
freq1 => counter[96].CLK
freq1 => counter[95].CLK
freq1 => counter[94].CLK
freq1 => counter[93].CLK
freq1 => counter[92].CLK
freq1 => counter[91].CLK
freq1 => counter[90].CLK
freq1 => counter[89].CLK
freq1 => counter[88].CLK
freq1 => counter[87].CLK
freq1 => counter[86].CLK
freq1 => counter[85].CLK
freq1 => counter[84].CLK
freq1 => counter[83].CLK
freq1 => counter[82].CLK
freq1 => counter[81].CLK
freq1 => counter[80].CLK
freq1 => counter[79].CLK
freq1 => counter[78].CLK
freq1 => counter[77].CLK
freq1 => counter[76].CLK
freq1 => counter[75].CLK
freq1 => counter[74].CLK
freq1 => counter[73].CLK
freq1 => counter[72].CLK
freq1 => counter[71].CLK
freq1 => counter[70].CLK
freq1 => counter[69].CLK
freq1 => counter[68].CLK
freq1 => counter[67].CLK
freq1 => counter[66].CLK
freq1 => counter[65].CLK
freq1 => counter[64].CLK
freq1 => counter[63].CLK
freq1 => counter[62].CLK
freq1 => counter[61].CLK
freq1 => counter[60].CLK
freq1 => counter[59].CLK
freq1 => counter[58].CLK
freq1 => counter[57].CLK
freq1 => counter[56].CLK
freq1 => counter[55].CLK
freq1 => counter[54].CLK
freq1 => counter[53].CLK
freq1 => counter[52].CLK
freq1 => counter[51].CLK
freq1 => counter[50].CLK
freq1 => counter[49].CLK
freq1 => counter[48].CLK
freq1 => counter[47].CLK
freq1 => counter[46].CLK
freq1 => counter[45].CLK
freq1 => counter[44].CLK
freq1 => counter[43].CLK
freq1 => counter[42].CLK
freq1 => counter[41].CLK
freq1 => counter[40].CLK
freq1 => counter[39].CLK
freq1 => counter[38].CLK
freq1 => counter[37].CLK
freq1 => counter[36].CLK
freq1 => counter[35].CLK
freq1 => counter[34].CLK
freq1 => counter[33].CLK
freq1 => counter[32].CLK
freq1 => counter[31].CLK
freq1 => counter[30].CLK
freq1 => counter[29].CLK
freq1 => counter[28].CLK
freq1 => counter[27].CLK
freq1 => counter[26].CLK
freq1 => counter[25].CLK
freq1 => counter[24].CLK
freq1 => counter[23].CLK
freq1 => counter[22].CLK
freq1 => counter[21].CLK
freq1 => counter[20].CLK
freq1 => counter[19].CLK
freq1 => counter[18].CLK
freq1 => counter[17].CLK
freq1 => counter[16].CLK
freq1 => counter[15].CLK
freq1 => counter[14].CLK
freq1 => counter[13].CLK
freq1 => counter[12].CLK
freq1 => counter[11].CLK
freq1 => counter[10].CLK
freq1 => counter[9].CLK
freq1 => counter[8].CLK
freq1 => counter[7].CLK
freq1 => counter[6].CLK
freq1 => counter[5].CLK
freq1 => counter[4].CLK
freq1 => counter[3].CLK
freq1 => counter[2].CLK
freq1 => counter[1].CLK
freq1 => counter[0].CLK
freq1 => freq2~reg0.CLK
rst => counter[100].ACLR
rst => counter[99].ACLR
rst => counter[98].ACLR
rst => counter[97].ACLR
rst => counter[96].ACLR
rst => counter[95].ACLR
rst => counter[94].ACLR
rst => counter[93].ACLR
rst => counter[92].ACLR
rst => counter[91].ACLR
rst => counter[90].ACLR
rst => counter[89].ACLR
rst => counter[88].ACLR
rst => counter[87].ACLR
rst => counter[86].ACLR
rst => counter[85].ACLR
rst => counter[84].ACLR
rst => counter[83].ACLR
rst => counter[82].ACLR
rst => counter[81].ACLR
rst => counter[80].ACLR
rst => counter[79].ACLR
rst => counter[78].ACLR
rst => counter[77].ACLR
rst => counter[76].ACLR
rst => counter[75].ACLR
rst => counter[74].ACLR
rst => counter[73].ACLR
rst => counter[72].ACLR
rst => counter[71].ACLR
rst => counter[70].ACLR
rst => counter[69].ACLR
rst => counter[68].ACLR
rst => counter[67].ACLR
rst => counter[66].ACLR
rst => counter[65].ACLR
rst => counter[64].ACLR
rst => counter[63].ACLR
rst => counter[62].ACLR
rst => counter[61].ACLR
rst => counter[60].ACLR
rst => counter[59].ACLR
rst => counter[58].ACLR
rst => counter[57].ACLR
rst => counter[56].ACLR
rst => counter[55].ACLR
rst => counter[54].ACLR
rst => counter[53].ACLR
rst => counter[52].ACLR
rst => counter[51].ACLR
rst => counter[50].ACLR
rst => counter[49].ACLR
rst => counter[48].ACLR
rst => counter[47].ACLR
rst => counter[46].ACLR
rst => counter[45].ACLR
rst => counter[44].ACLR
rst => counter[43].ACLR
rst => counter[42].ACLR
rst => counter[41].ACLR
rst => counter[40].ACLR
rst => counter[39].ACLR
rst => counter[38].ACLR
rst => counter[37].ACLR
rst => counter[36].ACLR
rst => counter[35].ACLR
rst => counter[34].ACLR
rst => counter[33].ACLR
rst => counter[32].ACLR
rst => counter[31].ACLR
rst => counter[30].ACLR
rst => counter[29].ACLR
rst => counter[28].ACLR
rst => counter[27].ACLR
rst => counter[26].ACLR
rst => counter[25].ACLR
rst => counter[24].ACLR
rst => counter[23].ACLR
rst => counter[22].ACLR
rst => counter[21].ACLR
rst => counter[20].ACLR
rst => counter[19].ACLR
rst => counter[18].ACLR
rst => counter[17].ACLR
rst => counter[16].ACLR
rst => counter[15].ACLR
rst => counter[14].ACLR
rst => counter[13].ACLR
rst => counter[12].ACLR
rst => counter[11].ACLR
rst => counter[10].ACLR
rst => counter[9].ACLR
rst => counter[8].ACLR
rst => counter[7].ACLR
rst => counter[6].ACLR
rst => counter[5].ACLR
rst => counter[4].ACLR
rst => counter[3].ACLR
rst => counter[2].ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => freq2~reg0.ACLR
freq2 <= freq2~reg0.DB_MAX_OUTPUT_PORT_TYPE


