{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 19:35:04 2010 " "Info: Processing started: Tue Apr 20 19:35:04 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP -c SIMCOMP " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP -c SIMCOMP" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"end\"; \"end\" without \"begin\"  SIMCOMP.v(64) " "Error (10170): Verilog HDL syntax error at SIMCOMP.v(64) near text \"end\"; \"end\" without \"begin\" " {  } { { "SIMCOMP.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/SIMCOMP.v" 64 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SIMCOMP.v(25) " "Warning (10268): Verilog HDL information at SIMCOMP.v(25): always construct contains both blocking and non-blocking assignments" {  } { { "SIMCOMP.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/SIMCOMP.v" 25 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR_EOF" ";  expecting an identifier SIMCOMP.v(65) " "Error (10171): Verilog HDL syntax error at SIMCOMP.v(65) near end of file ;  expecting an identifier" {  } { { "SIMCOMP.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SMPCOMP/SIMCOMP.v" 65 0 0 } }  } 0 10171 "Verilog HDL syntax error at %2!s! near end of file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIMCOMP.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file SIMCOMP.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Error: Peak virtual memory: 191 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Tue Apr 20 19:35:05 2010 " "Error: Processing ended: Tue Apr 20 19:35:05 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
