module SIMCOMP2(CLK, PC, R0, R1, R2, R3, IR, MBR, MAR);
input CLK;
//reg [15:0] R[0:3];
output R0,R1,R2,R3, PC, IR, MBR, MAR;
reg [15:0] MBR, IR, R0, R1, R2, R3;
reg [11:0] PC, MAR;
reg [3:0] state;
reg [15:0] R[0:3];
reg [15:0] Memory [0:63];

parameter load=4'b0011, store=4'b1011, add=4'b0111, jump=4'b0000;//jump=0000b

initial
  begin
  //instructions
  Memory[10]=16'h3103;
  Memory[11]=16'h3204;
  Memory[12]=16'h7580;
  Memory[13]=16'hB105;
  
  //data
  Memory[3] =16'hA;
  Memory[4] =16'h6;
  
  PC=10;
  state=0;
 end
always @(posedge CLK) begin
 
 case (state)
   0: begin
       MAR <= PC;
       state =1; 
      end
   1: begin //fetch instruction
       IR    <= Memory[MAR];
       state = 2;
       PC    <=PC +1;
      end
   2: begin //instruction decoding
       MAR <= IR[5:0];
       state=3;
      end
   3: begin //fetch operands
      // load and store deals for reg with index store in IR[9:8]
       state=4;
       case(IR[15:12])
        load : MBR <= Memory[MAR];
        //add  : ;
        store: MBR <= R[IR[9:8]];
        jump : begin 
                PC <= MAR;
                state=0; 
               end
       endcase
      end
   4: begin
       if(IR[15:12]==4'h7) begin//add
        R[IR[11:10]] <= R[IR[9:8]]+R[IR[7:6]];
        state=0;
       end
       else if(IR[15:12]==4'h3) begin//load
        R[IR[9:8]] <= MBR;
        state=0;
       end
       else if(IR[15:12]==4'hB) begin//store
        Memory[MAR] <= MBR;
        state=0;
       end
       
      end
 endcase
 R0<=R[0]; R1<=R[1];R2<=R[2];R3<=R[3];
 end
endmodule
