{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 21:41:38 2010 " "Info: Processing started: Thu Mar 18 21:41:38 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off complete -c complete " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off complete -c complete" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "complete.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file complete.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "complete.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 freq_div " "Info: Found entity 2: freq_div" {  } { { "complete.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.v" 30 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 sevenseg " "Info: Found entity 3: sevenseg" {  } { { "complete.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.v" 61 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "complete.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file complete.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 complete " "Info: Found entity 1: complete" {  } { { "complete.bdf" "" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "complete " "Info: Elaborating entity \"complete\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sevenseg sevenseg:inst4 " "Info: Elaborating entity \"sevenseg\" for hierarchy \"sevenseg:inst4\"" {  } { { "complete.bdf" "inst4" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.bdf" { { 96 528 656 192 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst\"" {  } { { "complete.bdf" "inst" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.bdf" { { 96 376 504 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 complete.v(16) " "Warning (10230): Verilog HDL assignment warning at complete.v(16): truncated value with size 32 to match size of target (4)" {  } { { "complete.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 complete.v(17) " "Warning (10230): Verilog HDL assignment warning at complete.v(17): truncated value with size 32 to match size of target (4)" {  } { { "complete.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq_div freq_div:inst3 " "Info: Elaborating entity \"freq_div\" for hierarchy \"freq_div:inst3\"" {  } { { "complete.bdf" "inst3" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.bdf" { { 80 208 304 176 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 complete.v(52) " "Warning (10230): Verilog HDL assignment warning at complete.v(52): truncated value with size 32 to match size of target (3)" {  } { { "complete.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/all - Copy/complete.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "25 " "Info: Implemented 25 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "197 " "Info: Peak virtual memory: 197 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 21:41:42 2010 " "Info: Processing ended: Thu Mar 18 21:41:42 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
