Classic Timing Analyzer report for complete
Thu Mar 18 21:42:54 2010
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'clock'
  7. tsu
  8. tco
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From              ; To                ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; -3.774 ns                                      ; reset             ; counter:inst|c[3] ; --         ; clock    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.006 ns                                      ; counter:inst|c[1] ; out[2]            ; clock      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 4.313 ns                                       ; reset             ; counter:inst|c[2] ; --         ; clock    ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[0] ; counter:inst|c[3] ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                   ;                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                       ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[0]         ; counter:inst|c[3]         ; clock      ; clock    ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[1]         ; counter:inst|c[2]         ; clock      ; clock    ; None                        ; None                      ; 1.275 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[0]         ; counter:inst|c[2]         ; clock      ; clock    ; None                        ; None                      ; 1.260 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[1] ; freq_div:inst3|freq2      ; clock      ; clock    ; None                        ; None                      ; 0.985 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[1]         ; counter:inst|c[3]         ; clock      ; clock    ; None                        ; None                      ; 1.103 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[2]         ; counter:inst|c[3]         ; clock      ; clock    ; None                        ; None                      ; 1.067 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[0] ; freq_div:inst3|counter[1] ; clock      ; clock    ; None                        ; None                      ; 1.028 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[0] ; freq_div:inst3|counter[2] ; clock      ; clock    ; None                        ; None                      ; 1.027 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[2] ; freq_div:inst3|counter[0] ; clock      ; clock    ; None                        ; None                      ; 0.984 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[0] ; freq_div:inst3|freq2      ; clock      ; clock    ; None                        ; None                      ; 0.745 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[0]         ; counter:inst|c[1]         ; clock      ; clock    ; None                        ; None                      ; 0.870 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[2] ; freq_div:inst3|freq2      ; clock      ; clock    ; None                        ; None                      ; 0.638 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[2] ; freq_div:inst3|counter[1] ; clock      ; clock    ; None                        ; None                      ; 0.638 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[1] ; freq_div:inst3|counter[0] ; clock      ; clock    ; None                        ; None                      ; 0.638 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[1] ; freq_div:inst3|counter[2] ; clock      ; clock    ; None                        ; None                      ; 0.638 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[0]         ; counter:inst|c[0]         ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[1] ; freq_div:inst3|counter[1] ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[0] ; freq_div:inst3|counter[0] ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; freq_div:inst3|counter[2] ; freq_div:inst3|counter[2] ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[1]         ; counter:inst|c[1]         ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[2]         ; counter:inst|c[2]         ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
; N/A   ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; counter:inst|c[3]         ; counter:inst|c[3]         ; clock      ; clock    ; None                        ; None                      ; 0.454 ns                ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------+
; tsu                                                                      ;
+-------+--------------+------------+-------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To                ; To Clock ;
+-------+--------------+------------+-------+-------------------+----------+
; N/A   ; None         ; -3.774 ns  ; reset ; counter:inst|c[1] ; clock    ;
; N/A   ; None         ; -3.774 ns  ; reset ; counter:inst|c[3] ; clock    ;
; N/A   ; None         ; -4.059 ns  ; reset ; counter:inst|c[0] ; clock    ;
; N/A   ; None         ; -4.065 ns  ; reset ; counter:inst|c[2] ; clock    ;
+-------+--------------+------------+-------+-------------------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+-------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To     ; From Clock ;
+-------+--------------+------------+-------------------+--------+------------+
; N/A   ; None         ; 13.006 ns  ; counter:inst|c[1] ; out[2] ; clock      ;
; N/A   ; None         ; 12.859 ns  ; counter:inst|c[3] ; out[2] ; clock      ;
; N/A   ; None         ; 12.769 ns  ; counter:inst|c[2] ; out[2] ; clock      ;
; N/A   ; None         ; 12.577 ns  ; counter:inst|c[0] ; out[2] ; clock      ;
; N/A   ; None         ; 12.269 ns  ; counter:inst|c[1] ; out[4] ; clock      ;
; N/A   ; None         ; 12.120 ns  ; counter:inst|c[3] ; out[4] ; clock      ;
; N/A   ; None         ; 12.083 ns  ; counter:inst|c[1] ; out[6] ; clock      ;
; N/A   ; None         ; 12.068 ns  ; counter:inst|c[2] ; out[4] ; clock      ;
; N/A   ; None         ; 11.931 ns  ; counter:inst|c[3] ; out[6] ; clock      ;
; N/A   ; None         ; 11.871 ns  ; counter:inst|c[2] ; out[6] ; clock      ;
; N/A   ; None         ; 11.835 ns  ; counter:inst|c[0] ; out[4] ; clock      ;
; N/A   ; None         ; 11.646 ns  ; counter:inst|c[0] ; out[6] ; clock      ;
; N/A   ; None         ; 11.620 ns  ; counter:inst|c[1] ; out[0] ; clock      ;
; N/A   ; None         ; 11.512 ns  ; counter:inst|c[3] ; out[0] ; clock      ;
; N/A   ; None         ; 11.457 ns  ; counter:inst|c[2] ; out[0] ; clock      ;
; N/A   ; None         ; 11.311 ns  ; counter:inst|c[1] ; out[5] ; clock      ;
; N/A   ; None         ; 11.309 ns  ; counter:inst|c[1] ; out[3] ; clock      ;
; N/A   ; None         ; 11.308 ns  ; counter:inst|c[1] ; out[1] ; clock      ;
; N/A   ; None         ; 11.225 ns  ; counter:inst|c[0] ; out[0] ; clock      ;
; N/A   ; None         ; 11.159 ns  ; counter:inst|c[3] ; out[5] ; clock      ;
; N/A   ; None         ; 11.157 ns  ; counter:inst|c[3] ; out[3] ; clock      ;
; N/A   ; None         ; 11.156 ns  ; counter:inst|c[3] ; out[1] ; clock      ;
; N/A   ; None         ; 11.101 ns  ; counter:inst|c[2] ; out[1] ; clock      ;
; N/A   ; None         ; 11.099 ns  ; counter:inst|c[2] ; out[3] ; clock      ;
; N/A   ; None         ; 11.098 ns  ; counter:inst|c[2] ; out[5] ; clock      ;
; N/A   ; None         ; 10.877 ns  ; counter:inst|c[0] ; out[5] ; clock      ;
; N/A   ; None         ; 10.875 ns  ; counter:inst|c[0] ; out[3] ; clock      ;
; N/A   ; None         ; 10.874 ns  ; counter:inst|c[0] ; out[1] ; clock      ;
+-------+--------------+------------+-------------------+--------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+-------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                ; To Clock ;
+---------------+-------------+-----------+-------+-------------------+----------+
; N/A           ; None        ; 4.313 ns  ; reset ; counter:inst|c[2] ; clock    ;
; N/A           ; None        ; 4.307 ns  ; reset ; counter:inst|c[0] ; clock    ;
; N/A           ; None        ; 4.022 ns  ; reset ; counter:inst|c[1] ; clock    ;
; N/A           ; None        ; 4.022 ns  ; reset ; counter:inst|c[3] ; clock    ;
+---------------+-------------+-----------+-------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Thu Mar 18 21:42:50 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off complete -c complete --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "freq_div:inst3|freq2" as buffer
Info: Clock "clock" Internal fmax is restricted to 380.08 MHz between source register "counter:inst|c[0]" and destination register "counter:inst|c[3]"
    Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N9; Fanout = 11; REG Node = 'counter:inst|c[0]'
            Info: 2: + IC(0.416 ns) + CELL(0.319 ns) = 0.735 ns; Loc. = LCCOMB_X1_Y8_N6; Fanout = 1; COMB Node = 'counter:inst|Add1~0'
            Info: 3: + IC(0.291 ns) + CELL(0.178 ns) = 1.204 ns; Loc. = LCCOMB_X1_Y8_N30; Fanout = 1; COMB Node = 'counter:inst|c~15'
            Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.300 ns; Loc. = LCFF_X1_Y8_N31; Fanout = 8; REG Node = 'counter:inst|c[3]'
            Info: Total cell delay = 0.593 ns ( 45.62 % )
            Info: Total interconnect delay = 0.707 ns ( 54.38 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 6.494 ns
                Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'clock'
                Info: 2: + IC(1.047 ns) + CELL(0.879 ns) = 2.952 ns; Loc. = LCFF_X11_Y13_N29; Fanout = 1; REG Node = 'freq_div:inst3|freq2'
                Info: 3: + IC(1.967 ns) + CELL(0.000 ns) = 4.919 ns; Loc. = CLKCTRL_G11; Fanout = 4; COMB Node = 'freq_div:inst3|freq2~clkctrl'
                Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 6.494 ns; Loc. = LCFF_X1_Y8_N31; Fanout = 8; REG Node = 'counter:inst|c[3]'
                Info: Total cell delay = 2.507 ns ( 38.60 % )
                Info: Total interconnect delay = 3.987 ns ( 61.40 % )
            Info: - Longest clock path from clock "clock" to source register is 6.494 ns
                Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'clock'
                Info: 2: + IC(1.047 ns) + CELL(0.879 ns) = 2.952 ns; Loc. = LCFF_X11_Y13_N29; Fanout = 1; REG Node = 'freq_div:inst3|freq2'
                Info: 3: + IC(1.967 ns) + CELL(0.000 ns) = 4.919 ns; Loc. = CLKCTRL_G11; Fanout = 4; COMB Node = 'freq_div:inst3|freq2~clkctrl'
                Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 6.494 ns; Loc. = LCFF_X1_Y8_N9; Fanout = 11; REG Node = 'counter:inst|c[0]'
                Info: Total cell delay = 2.507 ns ( 38.60 % )
                Info: Total interconnect delay = 3.987 ns ( 61.40 % )
        Info: + Micro clock to output delay of source is 0.277 ns
        Info: + Micro setup delay of destination is -0.038 ns
Info: tsu for register "counter:inst|c[1]" (data pin = "reset", clock pin = "clock") is -3.774 ns
    Info: + Longest pin to register delay is 2.758 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(1.175 ns) + CELL(0.461 ns) = 2.662 ns; Loc. = LCCOMB_X1_Y8_N10; Fanout = 1; COMB Node = 'counter:inst|c~13'
        Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.758 ns; Loc. = LCFF_X1_Y8_N11; Fanout = 10; REG Node = 'counter:inst|c[1]'
        Info: Total cell delay = 1.583 ns ( 57.40 % )
        Info: Total interconnect delay = 1.175 ns ( 42.60 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clock" to destination register is 6.494 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'clock'
        Info: 2: + IC(1.047 ns) + CELL(0.879 ns) = 2.952 ns; Loc. = LCFF_X11_Y13_N29; Fanout = 1; REG Node = 'freq_div:inst3|freq2'
        Info: 3: + IC(1.967 ns) + CELL(0.000 ns) = 4.919 ns; Loc. = CLKCTRL_G11; Fanout = 4; COMB Node = 'freq_div:inst3|freq2~clkctrl'
        Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 6.494 ns; Loc. = LCFF_X1_Y8_N11; Fanout = 10; REG Node = 'counter:inst|c[1]'
        Info: Total cell delay = 2.507 ns ( 38.60 % )
        Info: Total interconnect delay = 3.987 ns ( 61.40 % )
Info: tco from clock "clock" to destination pin "out[2]" through register "counter:inst|c[1]" is 13.006 ns
    Info: + Longest clock path from clock "clock" to source register is 6.494 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'clock'
        Info: 2: + IC(1.047 ns) + CELL(0.879 ns) = 2.952 ns; Loc. = LCFF_X11_Y13_N29; Fanout = 1; REG Node = 'freq_div:inst3|freq2'
        Info: 3: + IC(1.967 ns) + CELL(0.000 ns) = 4.919 ns; Loc. = CLKCTRL_G11; Fanout = 4; COMB Node = 'freq_div:inst3|freq2~clkctrl'
        Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 6.494 ns; Loc. = LCFF_X1_Y8_N11; Fanout = 10; REG Node = 'counter:inst|c[1]'
        Info: Total cell delay = 2.507 ns ( 38.60 % )
        Info: Total interconnect delay = 3.987 ns ( 61.40 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 6.235 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N11; Fanout = 10; REG Node = 'counter:inst|c[1]'
        Info: 2: + IC(0.657 ns) + CELL(0.516 ns) = 1.173 ns; Loc. = LCCOMB_X1_Y8_N24; Fanout = 1; COMB Node = 'sevenseg:inst4|WideOr4~0'
        Info: 3: + IC(2.046 ns) + CELL(3.016 ns) = 6.235 ns; Loc. = PIN_A3; Fanout = 0; PIN Node = 'out[2]'
        Info: Total cell delay = 3.532 ns ( 56.65 % )
        Info: Total interconnect delay = 2.703 ns ( 43.35 % )
Info: th for register "counter:inst|c[2]" (data pin = "reset", clock pin = "clock") is 4.313 ns
    Info: + Longest clock path from clock "clock" to destination register is 6.494 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'clock'
        Info: 2: + IC(1.047 ns) + CELL(0.879 ns) = 2.952 ns; Loc. = LCFF_X11_Y13_N29; Fanout = 1; REG Node = 'freq_div:inst3|freq2'
        Info: 3: + IC(1.967 ns) + CELL(0.000 ns) = 4.919 ns; Loc. = CLKCTRL_G11; Fanout = 4; COMB Node = 'freq_div:inst3|freq2~clkctrl'
        Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 6.494 ns; Loc. = LCFF_X1_Y8_N21; Fanout = 9; REG Node = 'counter:inst|c[2]'
        Info: Total cell delay = 2.507 ns ( 38.60 % )
        Info: Total interconnect delay = 3.987 ns ( 61.40 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 2.467 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(1.168 ns) + CELL(0.177 ns) = 2.371 ns; Loc. = LCCOMB_X1_Y8_N20; Fanout = 1; COMB Node = 'counter:inst|c~14'
        Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.467 ns; Loc. = LCFF_X1_Y8_N21; Fanout = 9; REG Node = 'counter:inst|c[2]'
        Info: Total cell delay = 1.299 ns ( 52.66 % )
        Info: Total interconnect delay = 1.168 ns ( 47.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 159 megabytes
    Info: Processing ended: Thu Mar 18 21:42:54 2010
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:03


