|complete
out[0] <= sevenseg:inst4.out[0]
out[1] <= sevenseg:inst4.out[1]
out[2] <= sevenseg:inst4.out[2]
out[3] <= sevenseg:inst4.out[3]
out[4] <= sevenseg:inst4.out[4]
out[5] <= sevenseg:inst4.out[5]
out[6] <= sevenseg:inst4.out[6]
clock => freq_div:inst3.freq1
reset => freq_div:inst3.rst
reset => counter:inst.reset


|complete|sevenseg:inst4
in[0] => Decoder0.IN3
in[1] => Decoder0.IN2
in[2] => Decoder0.IN1
in[3] => Decoder0.IN0
out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE


|complete|counter:inst
clk => count[3]~reg0.CLK
clk => count[2]~reg0.CLK
clk => count[1]~reg0.CLK
clk => count[0]~reg0.CLK
clk => c[3].CLK
clk => c[2].CLK
clk => c[1].CLK
clk => c[0].CLK
reset => c~7.OUTPUTSELECT
reset => c~6.OUTPUTSELECT
reset => c~5.OUTPUTSELECT
reset => c~4.OUTPUTSELECT
reset => count~7.OUTPUTSELECT
reset => count~6.OUTPUTSELECT
reset => count~5.OUTPUTSELECT
reset => count~4.OUTPUTSELECT
count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|complete|freq_div:inst3
freq1 => counter[2].CLK
freq1 => counter[1].CLK
freq1 => counter[0].CLK
freq1 => freq2~reg0.CLK
rst => counter[2].ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => freq2~reg0.ACLR
freq2 <= freq2~reg0.DB_MAX_OUTPUT_PORT_TYPE


