{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 14:19:19 2010 " "Info: Processing started: Wed Mar 24 14:19:19 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ex1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ex1 " "Info: Found entity 1: ex1" {  } { { "ex1.bdf" "" { Schematic "E:/university/Thirdyear2/DigitalLab/MYWORK/exp7/quartus/task1/ex1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"(\";  expecting an identifier, or \"module\", or \"macromodule\", or \"function\", or \"parameter\", or \"primitive\", or \"real\", or \"realtime\", or \"reg\", or \"specparam\", or \"task\", or \"time\", or \"integer\", or \"config\", or \"localparam\", or \"(*\", or \"include\", or \"library\" ex1.v(22) " "Error (10170): Verilog HDL syntax error at ex1.v(22) near text \"(\";  expecting an identifier, or \"module\", or \"macromodule\", or \"function\", or \"parameter\", or \"primitive\", or \"real\", or \"realtime\", or \"reg\", or \"specparam\", or \"task\", or \"time\", or \"integer\", or \"config\", or \"localparam\", or \"(*\", or \"include\", or \"library\"" {  } { { "ex1.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp7/quartus/task1/ex1.v" 22 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex1.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file ex1.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Error: Peak virtual memory: 192 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Wed Mar 24 14:19:20 2010 " "Error: Processing ended: Wed Mar 24 14:19:20 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
