{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 23 01:56:10 2010 " "Info: Processing started: Fri Apr 23 01:56:10 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP4 -c SIMCOMP4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP4 -c SIMCOMP4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SIMCOMP4.v(27) " "Warning (10268): Verilog HDL information at SIMCOMP4.v(27): always construct contains both blocking and non-blocking assignments" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 27 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIMCOMP4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SIMCOMP4.v" { { "Info" "ISGN_ENTITY_NAME" "1 SIMCOMP4 " "Info: Found entity 1: SIMCOMP4" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "PC packed SIMCOMP4.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(6): data type declaration for \"PC\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "PC SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"PC\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R0 packed SIMCOMP4.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(4): data type declaration for \"R0\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R0 SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"R0\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R1 packed SIMCOMP4.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(4): data type declaration for \"R1\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R1 SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"R1\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R2 packed SIMCOMP4.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(4): data type declaration for \"R2\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R2 SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"R2\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R3 packed SIMCOMP4.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(4): data type declaration for \"R3\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R3 SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"R3\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "IR packed SIMCOMP4.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(4): data type declaration for \"IR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "IR SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"IR\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "MBR packed SIMCOMP4.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(4): data type declaration for \"MBR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "MBR SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"MBR\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "MAR packed SIMCOMP4.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(6): data type declaration for \"MAR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "MAR SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"MAR\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "IOBR packed SIMCOMP4.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(5): data type declaration for \"IOBR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "IOBR SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"IOBR\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "IOAR packed SIMCOMP4.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP4.v(6): data type declaration for \"IOAR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "IOAR SIMCOMP4.v(3) " "Info (10151): Verilog HDL Declaration information at SIMCOMP4.v(3): \"IOAR\" is declared here" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "SIMCOMP4 " "Info: Elaborating entity \"SIMCOMP4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 SIMCOMP4.v(37) " "Warning (10230): Verilog HDL assignment warning at SIMCOMP4.v(37): truncated value with size 32 to match size of target (6)" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 SIMCOMP4.v(56) " "Warning (10230): Verilog HDL assignment warning at SIMCOMP4.v(56): truncated value with size 32 to match size of target (16)" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 56 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 8 SIMCOMP4.v(64) " "Warning (10230): Verilog HDL assignment warning at SIMCOMP4.v(64): truncated value with size 16 to match size of target (8)" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 8 SIMCOMP4.v(65) " "Warning (10230): Verilog HDL assignment warning at SIMCOMP4.v(65): truncated value with size 16 to match size of target (8)" {  } { { "SIMCOMP4.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "IOPT_UNINFERRED_RAM_SUMMARY" "1 " "Info: Found 1 instances of uninferred RAM logic" { { "Info" "IOPT_READ_LOGIC_IS_ASYNCHRONOUS" "Memory " "Info: RAM logic \"Memory\" is uninferred due to asynchronous read logic" {  } { { "SIMCOMP4.v" "Memory" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.v" 9 -1 0 } }  } 0 0 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! instances of uninferred RAM logic" 0 0 "" 0 -1}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "SIMCOMP4.ram0_SIMCOMP4_fb1d88df.hdl.mif " "Warning: Memory Initialization File or Hexadecimal (Intel-Format) File \"SIMCOMP4.ram0_SIMCOMP4_fb1d88df.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 0 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state~30 " "Info: Register \"state~30\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state~31 " "Info: Register \"state~31\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state~33 " "Info: Register \"state~33\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.map.smsg " "Info: Generated suppressed messages file E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP4/SIMCOMP4.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2261 " "Info: Implemented 2261 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "122 " "Info: Implemented 122 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "2138 " "Info: Implemented 2138 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "201 " "Info: Peak virtual memory: 201 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 23 01:56:21 2010 " "Info: Processing ended: Fri Apr 23 01:56:21 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Info: Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
