module counter (clk, reset, count);
input clk, reset;
wire clk, reset;
output [3:0] count;
reg [3:0] count;
reg [3:0]c;//counter =4
initial c=4'b0000;

always @(posedge clk) begin

if(reset==1)begin
 count=4'b0000;
 c=4'b0000;
 end
else if(c<=4'b1111) begin
 count= count+1;
 c=c+1;
 end
if (c==4'b0000) begin
  count=4'b0000;
  c=4'b0000;
  end
  
end
endmodule 