{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 30 21:41:25 2010 " "Info: Processing started: Tue Mar 30 21:41:25 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MyMux -c MyMux " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MyMux -c MyMux" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyMux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyMux.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyMux " "Info: Found entity 1: MyMux" {  } { { "MyMux.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/MyMux/MyMux.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "out MyMux.v(8) " "Error (10137): Verilog HDL Procedural Assignment error at MyMux.v(8): object \"out\" on left-hand side of assignment must have a variable data type" {  } { { "MyMux.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/MyMux/MyMux.v" 8 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "out MyMux.v(10) " "Error (10137): Verilog HDL Procedural Assignment error at MyMux.v(10): object \"out\" on left-hand side of assignment must have a variable data type" {  } { { "MyMux.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp9/quartus/MyMux/MyMux.v" 10 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Error: Peak virtual memory: 191 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 30 21:41:27 2010 " "Error: Processing ended: Tue Mar 30 21:41:27 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
