{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 20 16:32:14 2010 " "Info: Processing started: Sat Mar 20 16:32:14 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off booth -c booth " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off booth -c booth" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "booth.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file booth.v" { { "Info" "ISGN_ENTITY_NAME" "1 booth " "Info: Found entity 1: booth" {  } { { "booth.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/booth/booth.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "product packed booth.v(7) " "Warning (10227): Verilog HDL Port Declaration warning at booth.v(7): data type declaration for \"product\" declares packed dimensions but the port declaration declaration does not" {  } { { "booth.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/booth/booth.v" 7 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "product booth.v(5) " "Info (10151): Verilog HDL Declaration information at booth.v(5): \"product\" is declared here" {  } { { "booth.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/booth/booth.v" 5 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "booth " "Info: Elaborating entity \"booth\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 booth.v(38) " "Warning (10230): Verilog HDL assignment warning at booth.v(38): truncated value with size 32 to match size of target (4)" {  } { { "booth.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp8/quartus/booth/booth.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "116 " "Info: Implemented 116 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "81 " "Info: Implemented 81 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "197 " "Info: Peak virtual memory: 197 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 20 16:32:19 2010 " "Info: Processing ended: Sat Mar 20 16:32:19 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
