Classic Timing Analyzer report for MyMemory
Wed Mar 31 13:19:00 2010
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                  ;
+------------------------------+-------+---------------+-------------+---------------+--------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From          ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+---------------+--------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.266 ns    ; enable        ; MyDFF:inst|Q ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 10.009 ns   ; MyDFF:inst5|Q ; output[5]    ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.500 ns   ; D1            ; MyDFF:inst|Q ; --         ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;             ;               ;              ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+---------------+--------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+--------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To            ; To Clock ;
+-------+--------------+------------+--------+---------------+----------+
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst6|Q ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst5|Q ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst4|Q ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst3|Q ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst2|Q ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst1|Q ; CLK      ;
; N/A   ; None         ; 4.266 ns   ; enable ; MyDFF:inst|Q  ; CLK      ;
; N/A   ; None         ; 3.984 ns   ; D3     ; MyDFF:inst2|Q ; CLK      ;
; N/A   ; None         ; 3.976 ns   ; D5     ; MyDFF:inst4|Q ; CLK      ;
; N/A   ; None         ; 3.889 ns   ; D6     ; MyDFF:inst5|Q ; CLK      ;
; N/A   ; None         ; 3.859 ns   ; D4     ; MyDFF:inst3|Q ; CLK      ;
; N/A   ; None         ; 3.829 ns   ; D2     ; MyDFF:inst1|Q ; CLK      ;
; N/A   ; None         ; 3.824 ns   ; D7     ; MyDFF:inst6|Q ; CLK      ;
; N/A   ; None         ; 3.748 ns   ; D1     ; MyDFF:inst|Q  ; CLK      ;
+-------+--------------+------------+--------+---------------+----------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+---------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To        ; From Clock ;
+-------+--------------+------------+---------------+-----------+------------+
; N/A   ; None         ; 10.009 ns  ; MyDFF:inst5|Q ; output[5] ; CLK        ;
; N/A   ; None         ; 8.966 ns   ; MyDFF:inst3|Q ; output[3] ; CLK        ;
; N/A   ; None         ; 7.717 ns   ; MyDFF:inst1|Q ; output[1] ; CLK        ;
; N/A   ; None         ; 7.704 ns   ; MyDFF:inst2|Q ; output[2] ; CLK        ;
; N/A   ; None         ; 7.665 ns   ; MyDFF:inst4|Q ; output[4] ; CLK        ;
; N/A   ; None         ; 7.356 ns   ; MyDFF:inst|Q  ; output[0] ; CLK        ;
; N/A   ; None         ; 7.239 ns   ; MyDFF:inst6|Q ; output[6] ; CLK        ;
+-------+--------------+------------+---------------+-----------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+--------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To            ; To Clock ;
+---------------+-------------+-----------+--------+---------------+----------+
; N/A           ; None        ; -3.500 ns ; D1     ; MyDFF:inst|Q  ; CLK      ;
; N/A           ; None        ; -3.576 ns ; D7     ; MyDFF:inst6|Q ; CLK      ;
; N/A           ; None        ; -3.581 ns ; D2     ; MyDFF:inst1|Q ; CLK      ;
; N/A           ; None        ; -3.611 ns ; D4     ; MyDFF:inst3|Q ; CLK      ;
; N/A           ; None        ; -3.641 ns ; D6     ; MyDFF:inst5|Q ; CLK      ;
; N/A           ; None        ; -3.728 ns ; D5     ; MyDFF:inst4|Q ; CLK      ;
; N/A           ; None        ; -3.736 ns ; D3     ; MyDFF:inst2|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst6|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst5|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst4|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst3|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst2|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst1|Q ; CLK      ;
; N/A           ; None        ; -4.018 ns ; enable ; MyDFF:inst|Q  ; CLK      ;
+---------------+-------------+-----------+--------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Wed Mar 31 13:18:57 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MyMemory -c MyMemory --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CLK"
Info: tsu for register "MyDFF:inst6|Q" (data pin = "enable", clock pin = "CLK") is 4.266 ns
    Info: + Longest pin to register delay is 7.158 ns
        Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_R5; Fanout = 7; PIN Node = 'enable'
        Info: 2: + IC(5.556 ns) + CELL(0.758 ns) = 7.158 ns; Loc. = LCFF_X12_Y6_N9; Fanout = 1; REG Node = 'MyDFF:inst6|Q'
        Info: Total cell delay = 1.602 ns ( 22.38 % )
        Info: Total interconnect delay = 5.556 ns ( 77.62 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.854 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.854 ns; Loc. = LCFF_X12_Y6_N9; Fanout = 1; REG Node = 'MyDFF:inst6|Q'
        Info: Total cell delay = 1.628 ns ( 57.04 % )
        Info: Total interconnect delay = 1.226 ns ( 42.96 % )
Info: tco from clock "CLK" to destination pin "output[5]" through register "MyDFF:inst5|Q" is 10.009 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.854 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.854 ns; Loc. = LCFF_X12_Y6_N3; Fanout = 1; REG Node = 'MyDFF:inst5|Q'
        Info: Total cell delay = 1.628 ns ( 57.04 % )
        Info: Total interconnect delay = 1.226 ns ( 42.96 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 6.878 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y6_N3; Fanout = 1; REG Node = 'MyDFF:inst5|Q'
        Info: 2: + IC(4.028 ns) + CELL(2.850 ns) = 6.878 ns; Loc. = PIN_V22; Fanout = 0; PIN Node = 'output[5]'
        Info: Total cell delay = 2.850 ns ( 41.44 % )
        Info: Total interconnect delay = 4.028 ns ( 58.56 % )
Info: th for register "MyDFF:inst|Q" (data pin = "D1", clock pin = "CLK") is -3.500 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.854 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.854 ns; Loc. = LCFF_X12_Y6_N5; Fanout = 1; REG Node = 'MyDFF:inst|Q'
        Info: Total cell delay = 1.628 ns ( 57.04 % )
        Info: Total interconnect delay = 1.226 ns ( 42.96 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 6.640 ns
        Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_V1; Fanout = 1; PIN Node = 'D1'
        Info: 2: + IC(5.492 ns) + CELL(0.178 ns) = 6.544 ns; Loc. = LCCOMB_X12_Y6_N4; Fanout = 1; COMB Node = 'MyDFF:inst|Q~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.640 ns; Loc. = LCFF_X12_Y6_N5; Fanout = 1; REG Node = 'MyDFF:inst|Q'
        Info: Total cell delay = 1.148 ns ( 17.29 % )
        Info: Total interconnect delay = 5.492 ns ( 82.71 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 159 megabytes
    Info: Processing ended: Wed Mar 31 13:19:00 2010
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:01


