module SIMCOMP(CLK, PC, AC, IP, MBR, MAR);
input CLK;
output AC, PC, IP, MBR, MAR;
reg [15:0] AC, MBR, IP;
reg [11:0] PC, MAR;
reg [3:0] state;
reg [15:0] Memory [0:63];

parameter load=4'b0011, store=4'b1011, add=4'b0111;

initial
  begin
  //instructions
  Memory[10]=16'h3020;
  Memory[11]=16'h7021;
  Memory[12]=16'hB014;
  
  //data
  Memory[32]=16'hD7;
  Memory[33]=16'hD5;
  
  PC=10;
  state=0;
 end
always @(posedge CLK) begin
 case (state)
   0: begin
       MAR <= PC;
       state =1; 
      end
   1: begin //fetch instruction
       IP    <= Memory[MAR];
       state = 2;
       PC    <=PC +1;
      end
   2: begin //instruction decoding
       MAR <= IP[11:0];
       state=3;
      end
   3: begin //fetch operands
       state=4;
       case(IP[15:12])
        load : MBR <= Memory[MAR];
        add  : MBR <= Memory[MAR];
        store: MBR <= AC;
       endcase
      end
   4: begin
       if(IP[15:12]==4'h7) begin
        AC <= AC+MBR;
        state=0;
       end
       else if(IP[15:12]==4'h3) begin
        AC <= MBR;
        state=0;
       end
       else if(IP[15:12]==4'hB) begin
        Memory[MAR] <= MBR;
        state=0;
       end
      end
 endcase
 end
endmodule
