{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 19 04:46:54 2012 " "Info: Processing started: Mon Nov 19 04:46:54 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MYEncoder -c MYEncoder --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MYEncoder -c MYEncoder --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MYEncoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MYEncoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 MYEncoder " "Info: Found entity 1: MYEncoder" {  } { { "MYEncoder.v" "" { Text "C:/Documents and Settings/student/Desktop/Exp9/MYEncoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "MyDecoder.v(7) " "Warning (10268): Verilog HDL information at MyDecoder.v(7): always construct contains both blocking and non-blocking assignments" {  } { { "MyDecoder.v" "" { Text "C:/Documents and Settings/student/Desktop/Exp9/MyDecoder.v" 7 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyDecoder " "Info: Found entity 1: MyDecoder" {  } { { "MyDecoder.v" "" { Text "C:/Documents and Settings/student/Desktop/Exp9/MyDecoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "MYEncoder " "Info: Elaborating entity \"MYEncoder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 0 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Peak virtual memory: 165 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 19 04:46:55 2012 " "Info: Processing ended: Mon Nov 19 04:46:55 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
