{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 21:46:10 2010 " "Info: Processing started: Tue Apr 20 21:46:10 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP2 -c SIMCOMP2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIMCOMP2 -c SIMCOMP2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SIMCOMP2.v(28) " "Warning (10268): Verilog HDL information at SIMCOMP2.v(28): always construct contains both blocking and non-blocking assignments" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIMCOMP2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SIMCOMP2.v" { { "Info" "ISGN_ENTITY_NAME" "1 SIMCOMP2 " "Info: Found entity 1: SIMCOMP2" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "PC packed SIMCOMP2.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(6): data type declaration for \"PC\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "PC SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"PC\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R0 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R0\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R0 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R0\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R1 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R1\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R1 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R1\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R2 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R2\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R2 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R2\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "R3 packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"R3\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "R3 SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"R3\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "IR packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"IR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "IR SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"IR\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "MBR packed SIMCOMP2.v(5) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(5): data type declaration for \"MBR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 5 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "MBR SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"MBR\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "MAR packed SIMCOMP2.v(6) " "Warning (10227): Verilog HDL Port Declaration warning at SIMCOMP2.v(6): data type declaration for \"MAR\" declares packed dimensions but the port declaration declaration does not" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 6 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "MAR SIMCOMP2.v(4) " "Info (10151): Verilog HDL Declaration information at SIMCOMP2.v(4): \"MAR\" is declared here" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "SIMCOMP2 " "Info: Elaborating entity \"SIMCOMP2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 SIMCOMP2.v(38) " "Warning (10230): Verilog HDL assignment warning at SIMCOMP2.v(38): truncated value with size 32 to match size of target (12)" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "Memory~3 " "Warning: Inferred RAM node \"Memory~3\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "SIMCOMP2.v" "Memory~3" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 9 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0 -1}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "Memory~3 " "Info: Inferred altsyncram megafunction from the following design logic: \"Memory~3\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Info: Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 16 " "Info: Parameter WIDTH_A set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 6 " "Info: Parameter WIDTHAD_A set to 6" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 64 " "Info: Parameter NUMWORDS_A set to 64" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 16 " "Info: Parameter WIDTH_B set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 6 " "Info: Parameter WIDTHAD_B set to 6" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 64 " "Info: Parameter NUMWORDS_B set to 64" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Info: Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Info: Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Info: Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif " "Info: Parameter INIT_FILE set to db/SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1}  } { { "SIMCOMP2.v" "Memory~3" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 9 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:Memory_rtl_0 " "Info: Elaborated megafunction instantiation \"altsyncram:Memory_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altsyncram:Memory_rtl_0 " "Info: Instantiated megafunction \"altsyncram:Memory_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Info: Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 16 " "Info: Parameter \"WIDTH_A\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 6 " "Info: Parameter \"WIDTHAD_A\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 64 " "Info: Parameter \"NUMWORDS_A\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 16 " "Info: Parameter \"WIDTH_B\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 6 " "Info: Parameter \"WIDTHAD_B\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 64 " "Info: Parameter \"NUMWORDS_B\" = \"64\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Info: Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Info: Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Info: Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif " "Info: Parameter \"INIT_FILE\" = \"db/SIMCOMP2.ram0_SIMCOMP2_fb1d88d1.hdl.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sin1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sin1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sin1 " "Info: Found entity 1: altsyncram_sin1" {  } { { "db/altsyncram_sin1.tdf" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/db/altsyncram_sin1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state~20 " "Info: Register \"state~20\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state~21 " "Info: Register \"state~21\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state~23 " "Info: Register \"state~23\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.map.smsg " "Info: Generated suppressed messages file E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "507 " "Info: Implemented 507 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "120 " "Info: Implemented 120 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "370 " "Info: Implemented 370 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "198 " "Info: Peak virtual memory: 198 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 21:46:14 2010 " "Info: Processing ended: Tue Apr 20 21:46:14 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
