Classic Timing Analyzer report for SIMCOMP
Tue Apr 20 19:35:53 2010
Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'CLK'
  7. tco
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                           ;
+------------------------------+-------+---------------+----------------------------------+--------------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From               ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------------+-------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 11.213 ns                        ; IP[15]~reg0        ; IP[15]      ; CLK        ; --       ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 177.68 MHz ( period = 5.628 ns ) ; Memory_5_bypass[1] ; IP[15]~reg0 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                    ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------+-------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                   ; To                                                                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 177.68 MHz ( period = 5.628 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.389 ns                ;
; N/A                                     ; 177.90 MHz ( period = 5.621 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.382 ns                ;
; N/A                                     ; 178.16 MHz ( period = 5.613 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.372 ns                ;
; N/A                                     ; 179.12 MHz ( period = 5.583 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.276 ns                ;
; N/A                                     ; 179.12 MHz ( period = 5.583 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.276 ns                ;
; N/A                                     ; 179.12 MHz ( period = 5.583 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.276 ns                ;
; N/A                                     ; 179.12 MHz ( period = 5.583 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.276 ns                ;
; N/A                                     ; 179.12 MHz ( period = 5.583 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.276 ns                ;
; N/A                                     ; 179.12 MHz ( period = 5.583 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.276 ns                ;
; N/A                                     ; 179.15 MHz ( period = 5.582 ns )                    ; MAR[1]~reg0                                                                            ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.343 ns                ;
; N/A                                     ; 179.24 MHz ( period = 5.579 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.272 ns                ;
; N/A                                     ; 179.24 MHz ( period = 5.579 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.272 ns                ;
; N/A                                     ; 179.24 MHz ( period = 5.579 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.272 ns                ;
; N/A                                     ; 179.24 MHz ( period = 5.579 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.272 ns                ;
; N/A                                     ; 179.24 MHz ( period = 5.579 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.272 ns                ;
; N/A                                     ; 179.24 MHz ( period = 5.579 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.272 ns                ;
; N/A                                     ; 179.37 MHz ( period = 5.575 ns )                    ; MAR[1]~reg0                                                                            ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.336 ns                ;
; N/A                                     ; 179.50 MHz ( period = 5.571 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.262 ns                ;
; N/A                                     ; 179.50 MHz ( period = 5.571 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.262 ns                ;
; N/A                                     ; 179.50 MHz ( period = 5.571 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.262 ns                ;
; N/A                                     ; 179.50 MHz ( period = 5.571 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.262 ns                ;
; N/A                                     ; 179.50 MHz ( period = 5.571 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.262 ns                ;
; N/A                                     ; 179.50 MHz ( period = 5.571 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.262 ns                ;
; N/A                                     ; 179.63 MHz ( period = 5.567 ns )                    ; MAR[1]~reg0                                                                            ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.326 ns                ;
; N/A                                     ; 183.99 MHz ( period = 5.435 ns )                    ; MAR[0]~reg0                                                                            ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.196 ns                ;
; N/A                                     ; 184.16 MHz ( period = 5.430 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.191 ns                ;
; N/A                                     ; 184.20 MHz ( period = 5.429 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.122 ns                ;
; N/A                                     ; 184.20 MHz ( period = 5.429 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.122 ns                ;
; N/A                                     ; 184.20 MHz ( period = 5.429 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.122 ns                ;
; N/A                                     ; 184.20 MHz ( period = 5.429 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.122 ns                ;
; N/A                                     ; 184.20 MHz ( period = 5.429 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.122 ns                ;
; N/A                                     ; 184.20 MHz ( period = 5.429 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.122 ns                ;
; N/A                                     ; 184.23 MHz ( period = 5.428 ns )                    ; MAR[0]~reg0                                                                            ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.189 ns                ;
; N/A                                     ; 184.50 MHz ( period = 5.420 ns )                    ; MAR[0]~reg0                                                                            ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.179 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 5.086 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 5.086 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 5.086 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 5.086 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 5.086 ns                ;
; N/A                                     ; 185.32 MHz ( period = 5.396 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 5.086 ns                ;
; N/A                                     ; 185.74 MHz ( period = 5.384 ns )                    ; MAR[1]~reg0                                                                            ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.145 ns                ;
; N/A                                     ; 186.25 MHz ( period = 5.369 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.128 ns                ;
; N/A                                     ; 186.60 MHz ( period = 5.359 ns )                    ; MAR[3]~reg0                                                                            ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.120 ns                ;
; N/A                                     ; 186.85 MHz ( period = 5.352 ns )                    ; MAR[3]~reg0                                                                            ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.113 ns                ;
; N/A                                     ; 187.13 MHz ( period = 5.344 ns )                    ; MAR[3]~reg0                                                                            ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.103 ns                ;
; N/A                                     ; 187.51 MHz ( period = 5.333 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.024 ns                ;
; N/A                                     ; 187.51 MHz ( period = 5.333 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.024 ns                ;
; N/A                                     ; 187.51 MHz ( period = 5.333 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.024 ns                ;
; N/A                                     ; 187.51 MHz ( period = 5.333 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.024 ns                ;
; N/A                                     ; 187.51 MHz ( period = 5.333 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.024 ns                ;
; N/A                                     ; 187.51 MHz ( period = 5.333 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.024 ns                ;
; N/A                                     ; 187.86 MHz ( period = 5.323 ns )                    ; MAR[1]~reg0                                                                            ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.082 ns                ;
; N/A                                     ; 188.36 MHz ( period = 5.309 ns )                    ; Memory_5_bypass[9]                                                                     ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.069 ns                ;
; N/A                                     ; 188.61 MHz ( period = 5.302 ns )                    ; Memory_5_bypass[9]                                                                     ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.062 ns                ;
; N/A                                     ; 188.89 MHz ( period = 5.294 ns )                    ; Memory_5_bypass[9]                                                                     ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.052 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; MBR[0]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.967 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; MBR[0]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.967 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; MBR[0]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.967 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; MBR[0]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.967 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; MBR[0]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.967 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; MBR[0]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.967 ns                ;
; N/A                                     ; 189.29 MHz ( period = 5.283 ns )                    ; Memory_5_bypass[5]                                                                     ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.045 ns                ;
; N/A                                     ; 189.54 MHz ( period = 5.276 ns )                    ; Memory_5_bypass[5]                                                                     ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 5.038 ns                ;
; N/A                                     ; 189.83 MHz ( period = 5.268 ns )                    ; Memory_5_bypass[5]                                                                     ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 5.028 ns                ;
; N/A                                     ; 190.95 MHz ( period = 5.237 ns )                    ; MAR[0]~reg0                                                                            ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.998 ns                ;
; N/A                                     ; 191.09 MHz ( period = 5.233 ns )                    ; MAR[4]~reg0                                                                            ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.994 ns                ;
; N/A                                     ; 191.35 MHz ( period = 5.226 ns )                    ; MAR[4]~reg0                                                                            ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.987 ns                ;
; N/A                                     ; 191.64 MHz ( period = 5.218 ns )                    ; MAR[4]~reg0                                                                            ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.977 ns                ;
; N/A                                     ; 191.83 MHz ( period = 5.213 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.972 ns                ;
; N/A                                     ; 192.75 MHz ( period = 5.188 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; MBR[1]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.872 ns                ;
; N/A                                     ; 192.75 MHz ( period = 5.188 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; MBR[1]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.872 ns                ;
; N/A                                     ; 192.75 MHz ( period = 5.188 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; MBR[1]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.872 ns                ;
; N/A                                     ; 192.75 MHz ( period = 5.188 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; MBR[1]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.872 ns                ;
; N/A                                     ; 192.75 MHz ( period = 5.188 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; MBR[1]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.872 ns                ;
; N/A                                     ; 192.75 MHz ( period = 5.188 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; MBR[1]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.872 ns                ;
; N/A                                     ; 193.20 MHz ( period = 5.176 ns )                    ; MAR[0]~reg0                                                                            ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.935 ns                ;
; N/A                                     ; 193.54 MHz ( period = 5.167 ns )                    ; MAR[1]~reg0                                                                            ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.926 ns                ;
; N/A                                     ; 193.69 MHz ( period = 5.163 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.922 ns                ;
; N/A                                     ; 193.76 MHz ( period = 5.161 ns )                    ; MAR[3]~reg0                                                                            ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.922 ns                ;
; N/A                                     ; 194.06 MHz ( period = 5.153 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.844 ns                ;
; N/A                                     ; 194.06 MHz ( period = 5.153 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.844 ns                ;
; N/A                                     ; 194.06 MHz ( period = 5.153 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.844 ns                ;
; N/A                                     ; 194.06 MHz ( period = 5.153 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.844 ns                ;
; N/A                                     ; 194.06 MHz ( period = 5.153 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.844 ns                ;
; N/A                                     ; 194.06 MHz ( period = 5.153 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.844 ns                ;
; N/A                                     ; 194.25 MHz ( period = 5.148 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.839 ns                ;
; N/A                                     ; 194.25 MHz ( period = 5.148 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.839 ns                ;
; N/A                                     ; 194.25 MHz ( period = 5.148 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.839 ns                ;
; N/A                                     ; 194.25 MHz ( period = 5.148 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.839 ns                ;
; N/A                                     ; 194.25 MHz ( period = 5.148 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.839 ns                ;
; N/A                                     ; 194.25 MHz ( period = 5.148 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.839 ns                ;
; N/A                                     ; 195.24 MHz ( period = 5.122 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; MBR[3]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.806 ns                ;
; N/A                                     ; 195.24 MHz ( period = 5.122 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; MBR[3]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.806 ns                ;
; N/A                                     ; 195.24 MHz ( period = 5.122 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; MBR[3]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.806 ns                ;
; N/A                                     ; 195.24 MHz ( period = 5.122 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; MBR[3]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.806 ns                ;
; N/A                                     ; 195.24 MHz ( period = 5.122 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; MBR[3]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.806 ns                ;
; N/A                                     ; 195.24 MHz ( period = 5.122 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; MBR[3]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.806 ns                ;
; N/A                                     ; 195.43 MHz ( period = 5.117 ns )                    ; MAR[1]~reg0                                                                            ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.876 ns                ;
; N/A                                     ; 195.66 MHz ( period = 5.111 ns )                    ; Memory_5_bypass[9]                                                                     ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.871 ns                ;
; N/A                                     ; 195.81 MHz ( period = 5.107 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.798 ns                ;
; N/A                                     ; 195.81 MHz ( period = 5.107 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.798 ns                ;
; N/A                                     ; 195.81 MHz ( period = 5.107 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.798 ns                ;
; N/A                                     ; 195.81 MHz ( period = 5.107 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.798 ns                ;
; N/A                                     ; 195.81 MHz ( period = 5.107 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.798 ns                ;
; N/A                                     ; 195.81 MHz ( period = 5.107 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.798 ns                ;
; N/A                                     ; 195.92 MHz ( period = 5.104 ns )                    ; Memory_5_bypass[1]                                                                     ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.863 ns                ;
; N/A                                     ; 196.08 MHz ( period = 5.100 ns )                    ; MAR[3]~reg0                                                                            ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.859 ns                ;
; N/A                                     ; 196.66 MHz ( period = 5.085 ns )                    ; Memory_5_bypass[5]                                                                     ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.847 ns                ;
; N/A                                     ; 197.28 MHz ( period = 5.069 ns )                    ; MAR[5]~reg0                                                                            ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.830 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[3]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; CLK        ; CLK      ; None                        ; None                      ; 4.862 ns                ;
; N/A                                     ; 197.55 MHz ( period = 5.062 ns )                    ; MAR[5]~reg0                                                                            ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.823 ns                ;
; N/A                                     ; 197.71 MHz ( period = 5.058 ns )                    ; MAR[1]~reg0                                                                            ; IP[10]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.817 ns                ;
; N/A                                     ; 197.86 MHz ( period = 5.054 ns )                    ; MAR[5]~reg0                                                                            ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.813 ns                ;
; N/A                                     ; 198.02 MHz ( period = 5.050 ns )                    ; Memory_5_bypass[9]                                                                     ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.808 ns                ;
; N/A                                     ; 198.61 MHz ( period = 5.035 ns )                    ; MAR[4]~reg0                                                                            ; IP[7]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.796 ns                ;
; N/A                                     ; 199.04 MHz ( period = 5.024 ns )                    ; Memory_5_bypass[5]                                                                     ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.784 ns                ;
; N/A                                     ; 199.20 MHz ( period = 5.020 ns )                    ; MAR[0]~reg0                                                                            ; IP[13]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.779 ns                ;
; N/A                                     ; 200.56 MHz ( period = 4.986 ns )                    ; MAR[2]~reg0                                                                            ; IP[15]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.747 ns                ;
; N/A                                     ; 200.68 MHz ( period = 4.983 ns )                    ; Memory_5_bypass[1]                                                                     ; MBR[12]~reg0                                                                           ; CLK        ; CLK      ; None                        ; None                      ; 4.741 ns                ;
; N/A                                     ; 200.84 MHz ( period = 4.979 ns )                    ; MAR[2]~reg0                                                                            ; IP[14]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.740 ns                ;
; N/A                                     ; 201.05 MHz ( period = 4.974 ns )                    ; MAR[4]~reg0                                                                            ; IP[11]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.733 ns                ;
; N/A                                     ; 201.17 MHz ( period = 4.971 ns )                    ; MAR[2]~reg0                                                                            ; IP[8]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.730 ns                ;
; N/A                                     ; 201.21 MHz ( period = 4.970 ns )                    ; MAR[0]~reg0                                                                            ; IP[9]~reg0                                                                             ; CLK        ; CLK      ; None                        ; None                      ; 4.729 ns                ;
; N/A                                     ; 201.25 MHz ( period = 4.969 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; MBR[2]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.653 ns                ;
; N/A                                     ; 201.25 MHz ( period = 4.969 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; MBR[2]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.653 ns                ;
; N/A                                     ; 201.25 MHz ( period = 4.969 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; MBR[2]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.653 ns                ;
; N/A                                     ; 201.25 MHz ( period = 4.969 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; MBR[2]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.653 ns                ;
; N/A                                     ; 201.25 MHz ( period = 4.969 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; MBR[2]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.653 ns                ;
; N/A                                     ; 201.25 MHz ( period = 4.969 ns )                    ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; MBR[2]~reg0                                                                            ; CLK        ; CLK      ; None                        ; None                      ; 4.653 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[0]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 4.498 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0010                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; CLK        ; CLK      ; None                        ; None                      ; 4.496 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0000                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; CLK        ; CLK      ; None                        ; None                      ; 4.336 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0000                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 4.173 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0010                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 4.129 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; PC[3]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; CLK        ; CLK      ; None                        ; None                      ; 3.988 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0010                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; CLK        ; CLK      ; None                        ; None                      ; 3.776 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[3]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg3 ; CLK        ; CLK      ; None                        ; None                      ; 3.693 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[2]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; CLK        ; CLK      ; None                        ; None                      ; 3.646 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; PC[5]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; CLK        ; CLK      ; None                        ; None                      ; 3.642 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0000                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; CLK        ; CLK      ; None                        ; None                      ; 3.614 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[12]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_we_reg       ; CLK        ; CLK      ; None                        ; None                      ; 3.400 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; PC[0]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 3.409 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; PC[1]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[2]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; CLK        ; CLK      ; None                        ; None                      ; 3.293 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[0]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 3.265 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[13]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_we_reg       ; CLK        ; CLK      ; None                        ; None                      ; 3.171 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0000                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; CLK        ; CLK      ; None                        ; None                      ; 3.073 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0010                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 3.017 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; PC[2]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg2 ; CLK        ; CLK      ; None                        ; None                      ; 2.999 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[4]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; CLK        ; CLK      ; None                        ; None                      ; 2.969 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[5]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; CLK        ; CLK      ; None                        ; None                      ; 2.880 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg0  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg1  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a1~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg2  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a2~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg3  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a3~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg4  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a4~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg5  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a5~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg6  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a6~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg7  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a7~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg8  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a8~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg9  ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a9~porta_memory_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg10 ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a10~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg11 ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a11~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg12 ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a12~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg13 ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a13~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg14 ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a14~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg15 ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a15~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.780 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0010                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; CLK        ; CLK      ; None                        ; None                      ; 2.863 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[1]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 2.859 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[5]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; CLK        ; CLK      ; None                        ; None                      ; 2.774 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0000                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 2.754 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; PC[4]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; CLK        ; CLK      ; None                        ; None                      ; 2.708 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[4]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; CLK        ; CLK      ; None                        ; None                      ; 2.631 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0000                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg4 ; CLK        ; CLK      ; None                        ; None                      ; 2.590 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0010                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg5 ; CLK        ; CLK      ; None                        ; None                      ; 2.574 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[1]~reg0                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~portb_address_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 2.452 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; state.0100                                                                             ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_we_reg       ; CLK        ; CLK      ; None                        ; None                      ; 2.166 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[14]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_we_reg       ; CLK        ; CLK      ; None                        ; None                      ; 2.149 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[9]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg9  ; CLK        ; CLK      ; None                        ; None                      ; 2.140 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[11]~reg0                                                                           ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg11 ; CLK        ; CLK      ; None                        ; None                      ; 2.076 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[3]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_address_reg3 ; CLK        ; CLK      ; None                        ; None                      ; 1.885 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[4]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_address_reg4 ; CLK        ; CLK      ; None                        ; None                      ; 1.852 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; IP[15]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_we_reg       ; CLK        ; CLK      ; None                        ; None                      ; 1.671 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[2]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_address_reg2 ; CLK        ; CLK      ; None                        ; None                      ; 1.492 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[1]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_address_reg1 ; CLK        ; CLK      ; None                        ; None                      ; 1.479 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[10]~reg0                                                                           ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg10 ; CLK        ; CLK      ; None                        ; None                      ; 1.212 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[0]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_address_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 1.189 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MAR[5]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_address_reg5 ; CLK        ; CLK      ; None                        ; None                      ; 1.182 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[7]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg7  ; CLK        ; CLK      ; None                        ; None                      ; 1.156 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[8]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg8  ; CLK        ; CLK      ; None                        ; None                      ; 1.145 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[3]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLK        ; CLK      ; None                        ; None                      ; 1.149 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[15]~reg0                                                                           ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg15 ; CLK        ; CLK      ; None                        ; None                      ; 1.142 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[12]~reg0                                                                           ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg12 ; CLK        ; CLK      ; None                        ; None                      ; 1.140 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[14]~reg0                                                                           ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg14 ; CLK        ; CLK      ; None                        ; None                      ; 1.133 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[13]~reg0                                                                           ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg13 ; CLK        ; CLK      ; None                        ; None                      ; 1.132 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[0]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 1.121 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[2]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLK        ; CLK      ; None                        ; None                      ; 0.842 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[1]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLK        ; CLK      ; None                        ; None                      ; 0.835 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[6]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg6  ; CLK        ; CLK      ; None                        ; None                      ; 0.820 ns                ;
; N/A                                     ; Restricted to 195.01 MHz ( period = 5.128 ns )      ; MBR[5]~reg0                                                                            ; altsyncram:Memory_rtl_0|altsyncram_qcn1:auto_generated|ram_block1a0~porta_datain_reg5  ; CLK        ; CLK      ; None                        ; None                      ; 0.814 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                        ;                                                                                        ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 11.213 ns  ; IP[15]~reg0  ; IP[15]  ; CLK        ;
; N/A   ; None         ; 9.102 ns   ; IP[11]~reg0  ; IP[11]  ; CLK        ;
; N/A   ; None         ; 8.790 ns   ; AC[6]~reg0   ; AC[6]   ; CLK        ;
; N/A   ; None         ; 8.774 ns   ; IP[9]~reg0   ; IP[9]   ; CLK        ;
; N/A   ; None         ; 8.753 ns   ; AC[1]~reg0   ; AC[1]   ; CLK        ;
; N/A   ; None         ; 8.734 ns   ; PC[2]~reg0   ; PC[2]   ; CLK        ;
; N/A   ; None         ; 8.721 ns   ; IP[14]~reg0  ; IP[14]  ; CLK        ;
; N/A   ; None         ; 8.685 ns   ; MAR[10]~reg0 ; MAR[10] ; CLK        ;
; N/A   ; None         ; 8.405 ns   ; PC[11]~reg0  ; PC[11]  ; CLK        ;
; N/A   ; None         ; 8.395 ns   ; AC[12]~reg0  ; AC[12]  ; CLK        ;
; N/A   ; None         ; 8.387 ns   ; AC[10]~reg0  ; AC[10]  ; CLK        ;
; N/A   ; None         ; 8.086 ns   ; MAR[0]~reg0  ; MAR[0]  ; CLK        ;
; N/A   ; None         ; 8.047 ns   ; MBR[13]~reg0 ; MBR[13] ; CLK        ;
; N/A   ; None         ; 8.032 ns   ; MAR[3]~reg0  ; MAR[3]  ; CLK        ;
; N/A   ; None         ; 8.028 ns   ; MBR[1]~reg0  ; MBR[1]  ; CLK        ;
; N/A   ; None         ; 7.992 ns   ; MBR[11]~reg0 ; MBR[11] ; CLK        ;
; N/A   ; None         ; 7.988 ns   ; MBR[10]~reg0 ; MBR[10] ; CLK        ;
; N/A   ; None         ; 7.902 ns   ; AC[14]~reg0  ; AC[14]  ; CLK        ;
; N/A   ; None         ; 7.885 ns   ; PC[9]~reg0   ; PC[9]   ; CLK        ;
; N/A   ; None         ; 7.876 ns   ; AC[4]~reg0   ; AC[4]   ; CLK        ;
; N/A   ; None         ; 7.875 ns   ; PC[3]~reg0   ; PC[3]   ; CLK        ;
; N/A   ; None         ; 7.872 ns   ; MBR[15]~reg0 ; MBR[15] ; CLK        ;
; N/A   ; None         ; 7.871 ns   ; AC[3]~reg0   ; AC[3]   ; CLK        ;
; N/A   ; None         ; 7.866 ns   ; AC[0]~reg0   ; AC[0]   ; CLK        ;
; N/A   ; None         ; 7.857 ns   ; AC[2]~reg0   ; AC[2]   ; CLK        ;
; N/A   ; None         ; 7.856 ns   ; MBR[9]~reg0  ; MBR[9]  ; CLK        ;
; N/A   ; None         ; 7.842 ns   ; PC[0]~reg0   ; PC[0]   ; CLK        ;
; N/A   ; None         ; 7.832 ns   ; IP[3]~reg0   ; IP[3]   ; CLK        ;
; N/A   ; None         ; 7.808 ns   ; IP[4]~reg0   ; IP[4]   ; CLK        ;
; N/A   ; None         ; 7.802 ns   ; AC[7]~reg0   ; AC[7]   ; CLK        ;
; N/A   ; None         ; 7.745 ns   ; IP[5]~reg0   ; IP[5]   ; CLK        ;
; N/A   ; None         ; 7.714 ns   ; MBR[0]~reg0  ; MBR[0]  ; CLK        ;
; N/A   ; None         ; 7.705 ns   ; MBR[2]~reg0  ; MBR[2]  ; CLK        ;
; N/A   ; None         ; 7.698 ns   ; MBR[14]~reg0 ; MBR[14] ; CLK        ;
; N/A   ; None         ; 7.689 ns   ; MBR[5]~reg0  ; MBR[5]  ; CLK        ;
; N/A   ; None         ; 7.681 ns   ; MBR[3]~reg0  ; MBR[3]  ; CLK        ;
; N/A   ; None         ; 7.673 ns   ; MBR[4]~reg0  ; MBR[4]  ; CLK        ;
; N/A   ; None         ; 7.638 ns   ; AC[13]~reg0  ; AC[13]  ; CLK        ;
; N/A   ; None         ; 7.606 ns   ; AC[8]~reg0   ; AC[8]   ; CLK        ;
; N/A   ; None         ; 7.597 ns   ; IP[2]~reg0   ; IP[2]   ; CLK        ;
; N/A   ; None         ; 7.577 ns   ; MBR[7]~reg0  ; MBR[7]  ; CLK        ;
; N/A   ; None         ; 7.570 ns   ; IP[6]~reg0   ; IP[6]   ; CLK        ;
; N/A   ; None         ; 7.568 ns   ; MBR[6]~reg0  ; MBR[6]  ; CLK        ;
; N/A   ; None         ; 7.563 ns   ; PC[1]~reg0   ; PC[1]   ; CLK        ;
; N/A   ; None         ; 7.554 ns   ; IP[12]~reg0  ; IP[12]  ; CLK        ;
; N/A   ; None         ; 7.541 ns   ; MBR[8]~reg0  ; MBR[8]  ; CLK        ;
; N/A   ; None         ; 7.536 ns   ; IP[7]~reg0   ; IP[7]   ; CLK        ;
; N/A   ; None         ; 7.533 ns   ; PC[4]~reg0   ; PC[4]   ; CLK        ;
; N/A   ; None         ; 7.489 ns   ; PC[5]~reg0   ; PC[5]   ; CLK        ;
; N/A   ; None         ; 7.461 ns   ; IP[10]~reg0  ; IP[10]  ; CLK        ;
; N/A   ; None         ; 7.424 ns   ; AC[5]~reg0   ; AC[5]   ; CLK        ;
; N/A   ; None         ; 7.421 ns   ; AC[15]~reg0  ; AC[15]  ; CLK        ;
; N/A   ; None         ; 7.416 ns   ; MAR[9]~reg0  ; MAR[9]  ; CLK        ;
; N/A   ; None         ; 7.410 ns   ; MAR[2]~reg0  ; MAR[2]  ; CLK        ;
; N/A   ; None         ; 7.408 ns   ; IP[8]~reg0   ; IP[8]   ; CLK        ;
; N/A   ; None         ; 7.401 ns   ; MAR[4]~reg0  ; MAR[4]  ; CLK        ;
; N/A   ; None         ; 7.373 ns   ; MAR[8]~reg0  ; MAR[8]  ; CLK        ;
; N/A   ; None         ; 7.371 ns   ; MAR[11]~reg0 ; MAR[11] ; CLK        ;
; N/A   ; None         ; 7.370 ns   ; MAR[1]~reg0  ; MAR[1]  ; CLK        ;
; N/A   ; None         ; 7.366 ns   ; MAR[6]~reg0  ; MAR[6]  ; CLK        ;
; N/A   ; None         ; 7.351 ns   ; IP[1]~reg0   ; IP[1]   ; CLK        ;
; N/A   ; None         ; 7.326 ns   ; AC[11]~reg0  ; AC[11]  ; CLK        ;
; N/A   ; None         ; 7.310 ns   ; PC[8]~reg0   ; PC[8]   ; CLK        ;
; N/A   ; None         ; 7.294 ns   ; PC[10]~reg0  ; PC[10]  ; CLK        ;
; N/A   ; None         ; 7.292 ns   ; PC[6]~reg0   ; PC[6]   ; CLK        ;
; N/A   ; None         ; 7.285 ns   ; PC[7]~reg0   ; PC[7]   ; CLK        ;
; N/A   ; None         ; 7.281 ns   ; MAR[5]~reg0  ; MAR[5]  ; CLK        ;
; N/A   ; None         ; 7.281 ns   ; AC[9]~reg0   ; AC[9]   ; CLK        ;
; N/A   ; None         ; 7.274 ns   ; MBR[12]~reg0 ; MBR[12] ; CLK        ;
; N/A   ; None         ; 7.240 ns   ; IP[0]~reg0   ; IP[0]   ; CLK        ;
; N/A   ; None         ; 7.122 ns   ; MAR[7]~reg0  ; MAR[7]  ; CLK        ;
; N/A   ; None         ; 7.071 ns   ; IP[13]~reg0  ; IP[13]  ; CLK        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Tue Apr 20 19:35:52 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SIMCOMP -c SIMCOMP --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 177.68 MHz between source register "Memory_5_bypass[1]" and destination register "IP[15]~reg0" (period= 5.628 ns)
    Info: + Longest register to register delay is 5.389 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y21_N7; Fanout = 1; REG Node = 'Memory_5_bypass[1]'
        Info: 2: + IC(0.594 ns) + CELL(0.521 ns) = 1.115 ns; Loc. = LCCOMB_X45_Y21_N10; Fanout = 1; COMB Node = 'Memory~8'
        Info: 3: + IC(1.119 ns) + CELL(0.491 ns) = 2.725 ns; Loc. = LCCOMB_X40_Y21_N6; Fanout = 16; COMB Node = 'Memory~9'
        Info: 4: + IC(0.901 ns) + CELL(0.544 ns) = 4.170 ns; Loc. = LCCOMB_X42_Y21_N8; Fanout = 2; COMB Node = 'MBR[15]~16'
        Info: 5: + IC(0.806 ns) + CELL(0.413 ns) = 5.389 ns; Loc. = LCFF_X45_Y21_N3; Fanout = 21; REG Node = 'IP[15]~reg0'
        Info: Total cell delay = 1.969 ns ( 36.54 % )
        Info: Total interconnect delay = 3.420 ns ( 63.46 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.853 ns
            Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 145; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X45_Y21_N3; Fanout = 21; REG Node = 'IP[15]~reg0'
            Info: Total cell delay = 1.628 ns ( 57.06 % )
            Info: Total interconnect delay = 1.225 ns ( 42.94 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.853 ns
            Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 145; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X45_Y21_N7; Fanout = 1; REG Node = 'Memory_5_bypass[1]'
            Info: Total cell delay = 1.628 ns ( 57.06 % )
            Info: Total interconnect delay = 1.225 ns ( 42.94 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Micro setup delay of destination is -0.038 ns
Info: tco from clock "CLK" to destination pin "IP[15]" through register "IP[15]~reg0" is 11.213 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.853 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 145; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X45_Y21_N3; Fanout = 21; REG Node = 'IP[15]~reg0'
        Info: Total cell delay = 1.628 ns ( 57.06 % )
        Info: Total interconnect delay = 1.225 ns ( 42.94 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 8.083 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y21_N3; Fanout = 21; REG Node = 'IP[15]~reg0'
        Info: 2: + IC(5.253 ns) + CELL(2.830 ns) = 8.083 ns; Loc. = PIN_H4; Fanout = 0; PIN Node = 'IP[15]'
        Info: Total cell delay = 2.830 ns ( 35.01 % )
        Info: Total interconnect delay = 5.253 ns ( 64.99 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 160 megabytes
    Info: Processing ended: Tue Apr 20 19:35:53 2010
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


