Version 9.0 Build 132 02/25/2009 SJ Web Edition
11
980
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
MyMemory
# storage
db|MyMemory.(0).cnf
db|MyMemory.(0).cnf
# case_insensitive
# source_file
MyMemory.bdf
216594b4cca81bdbfbe650b5f07b89
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
MyDFF
# storage
db|MyMemory.(1).cnf
db|MyMemory.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDFF.v
eedbb36a380747457e28348e967e1
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
MyDFF:inst
MyDFF:inst1
MyDFF:inst2
MyDFF:inst3
MyDFF:inst4
MyDFF:inst5
MyDFF:inst6
}
# macro_sequence

# end
# entity
MyMux
# storage
db|MyMemory.(2).cnf
db|MyMemory.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyMux.v
6963f11beb40dda7dd58a578967f45
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
MyMux:inst7
MyMux:inst8
MyMux:inst9
MyMux:inst10
MyMux:inst11
MyMux:inst12
MyMux:inst13
}
# macro_sequence

# end
# complete

