{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 21:46:15 2010 " "Info: Processing started: Tue Apr 20 21:46:15 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off SIMCOMP2 -c SIMCOMP2 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SIMCOMP2 -c SIMCOMP2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "SIMCOMP2 EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"SIMCOMP2\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is not available with your current license" {  } {  } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "121 121 " "Warning: No exact pin location assignment(s) for 121 pins of 121 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[0\] " "Info: Pin PC\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[1\] " "Info: Pin PC\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[2\] " "Info: Pin PC\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[3\] " "Info: Pin PC\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[4\] " "Info: Pin PC\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[5\] " "Info: Pin PC\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[6\] " "Info: Pin PC\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[7\] " "Info: Pin PC\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[8\] " "Info: Pin PC\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[9\] " "Info: Pin PC\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[10\] " "Info: Pin PC\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PC\[11\] " "Info: Pin PC\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { PC[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[0\] " "Info: Pin R0\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[1\] " "Info: Pin R0\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[2\] " "Info: Pin R0\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[3\] " "Info: Pin R0\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[4\] " "Info: Pin R0\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[5\] " "Info: Pin R0\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[6\] " "Info: Pin R0\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[7\] " "Info: Pin R0\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[8\] " "Info: Pin R0\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[9\] " "Info: Pin R0\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[10\] " "Info: Pin R0\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[11\] " "Info: Pin R0\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[12\] " "Info: Pin R0\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[12] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[13\] " "Info: Pin R0\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[13] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[14\] " "Info: Pin R0\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[14] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R0\[15\] " "Info: Pin R0\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R0[15] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[0\] " "Info: Pin R1\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[1\] " "Info: Pin R1\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[2\] " "Info: Pin R1\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[3\] " "Info: Pin R1\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[4\] " "Info: Pin R1\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[5\] " "Info: Pin R1\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[6\] " "Info: Pin R1\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[7\] " "Info: Pin R1\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[8\] " "Info: Pin R1\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[9\] " "Info: Pin R1\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[10\] " "Info: Pin R1\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[11\] " "Info: Pin R1\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[12\] " "Info: Pin R1\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[12] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[13\] " "Info: Pin R1\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[13] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[14\] " "Info: Pin R1\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[14] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R1\[15\] " "Info: Pin R1\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R1[15] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[0\] " "Info: Pin R2\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[1\] " "Info: Pin R2\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[2\] " "Info: Pin R2\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[3\] " "Info: Pin R2\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[4\] " "Info: Pin R2\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[5\] " "Info: Pin R2\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[6\] " "Info: Pin R2\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[7\] " "Info: Pin R2\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[8\] " "Info: Pin R2\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[9\] " "Info: Pin R2\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[10\] " "Info: Pin R2\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[11\] " "Info: Pin R2\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[12\] " "Info: Pin R2\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[12] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[13\] " "Info: Pin R2\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[13] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[14\] " "Info: Pin R2\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[14] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R2\[15\] " "Info: Pin R2\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R2[15] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R2[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[0\] " "Info: Pin R3\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[1\] " "Info: Pin R3\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[2\] " "Info: Pin R3\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[3\] " "Info: Pin R3\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[4\] " "Info: Pin R3\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[5\] " "Info: Pin R3\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[6\] " "Info: Pin R3\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[7\] " "Info: Pin R3\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[8\] " "Info: Pin R3\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[9\] " "Info: Pin R3\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[10\] " "Info: Pin R3\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[11\] " "Info: Pin R3\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[12\] " "Info: Pin R3\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[12] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[13\] " "Info: Pin R3\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[13] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[14\] " "Info: Pin R3\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[14] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R3\[15\] " "Info: Pin R3\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { R3[15] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R3[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[0\] " "Info: Pin IR\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[1\] " "Info: Pin IR\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[2\] " "Info: Pin IR\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[3\] " "Info: Pin IR\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[4\] " "Info: Pin IR\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[5\] " "Info: Pin IR\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[6\] " "Info: Pin IR\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[7\] " "Info: Pin IR\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[8\] " "Info: Pin IR\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[9\] " "Info: Pin IR\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[10\] " "Info: Pin IR\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[11\] " "Info: Pin IR\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[12\] " "Info: Pin IR\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[12] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[13\] " "Info: Pin IR\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[13] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[14\] " "Info: Pin IR\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[14] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IR\[15\] " "Info: Pin IR\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { IR[15] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[0\] " "Info: Pin MBR\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[1\] " "Info: Pin MBR\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[2\] " "Info: Pin MBR\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[3\] " "Info: Pin MBR\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[4\] " "Info: Pin MBR\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[5\] " "Info: Pin MBR\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[6\] " "Info: Pin MBR\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[7\] " "Info: Pin MBR\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[8\] " "Info: Pin MBR\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[9\] " "Info: Pin MBR\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[10\] " "Info: Pin MBR\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[11\] " "Info: Pin MBR\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[12\] " "Info: Pin MBR\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[12] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[13\] " "Info: Pin MBR\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[13] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[14\] " "Info: Pin MBR\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[14] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MBR\[15\] " "Info: Pin MBR\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MBR[15] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MBR[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[0\] " "Info: Pin MAR\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[0] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[1\] " "Info: Pin MAR\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[1] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[2\] " "Info: Pin MAR\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[2] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[3\] " "Info: Pin MAR\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[3] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[4\] " "Info: Pin MAR\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[4] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[5\] " "Info: Pin MAR\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[5] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[6\] " "Info: Pin MAR\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[6] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[7\] " "Info: Pin MAR\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[7] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[8\] " "Info: Pin MAR\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[8] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[9\] " "Info: Pin MAR\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[9] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[10\] " "Info: Pin MAR\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[10] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MAR\[11\] " "Info: Pin MAR\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { MAR[11] } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { MAR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { CLK } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node CLK (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { CLK } } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "120 unused 3.3V 0 120 0 " "Info: Number of I/O pins in group: 120 (unused VREF, 3.3V VCCIO, 0 input, 120 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 40 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 31 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  31 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register R\[0\]\[2\] register R\[1\]\[15\] -7.273 ns " "Info: Slack time is -7.273 ns between source register \"R\[0\]\[2\]\" and destination register \"R\[1\]\[15\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.761 ns + Largest register register " "Info: + Largest register to register requirement is 0.761 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.608 ns   Shortest register " "Info:   Shortest clock path from clock \"CLK\" to destination register is 2.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.783 ns) 0.783 ns CLK 1 CLK Unassigned 1 " "Info: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.235 ns) + CELL(0.000 ns) 1.018 ns CLK~clkctrl 2 COMB Unassigned 452 " "Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 452; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.235 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 2.608 ns R\[1\]\[15\] 3 REG Unassigned 3 " "Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.608 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'R\[1\]\[15\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { CLK~clkctrl R[1][15] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 53.11 % ) " "Info: Total cell delay = 1.385 ns ( 53.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.223 ns ( 46.89 % ) " "Info: Total interconnect delay = 1.223 ns ( 46.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.608 ns   Longest register " "Info:   Longest clock path from clock \"CLK\" to destination register is 2.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.783 ns) 0.783 ns CLK 1 CLK Unassigned 1 " "Info: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.235 ns) + CELL(0.000 ns) 1.018 ns CLK~clkctrl 2 COMB Unassigned 452 " "Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 452; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.235 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 2.608 ns R\[1\]\[15\] 3 REG Unassigned 3 " "Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.608 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'R\[1\]\[15\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { CLK~clkctrl R[1][15] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 53.11 % ) " "Info: Total cell delay = 1.385 ns ( 53.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.223 ns ( 46.89 % ) " "Info: Total interconnect delay = 1.223 ns ( 46.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.608 ns   Shortest register " "Info:   Shortest clock path from clock \"CLK\" to source register is 2.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.783 ns) 0.783 ns CLK 1 CLK Unassigned 1 " "Info: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.235 ns) + CELL(0.000 ns) 1.018 ns CLK~clkctrl 2 COMB Unassigned 452 " "Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 452; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.235 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 2.608 ns R\[0\]\[2\] 3 REG Unassigned 3 " "Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.608 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'R\[0\]\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { CLK~clkctrl R[0][2] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 53.11 % ) " "Info: Total cell delay = 1.385 ns ( 53.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.223 ns ( 46.89 % ) " "Info: Total interconnect delay = 1.223 ns ( 46.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.608 ns   Longest register " "Info:   Longest clock path from clock \"CLK\" to source register is 2.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.783 ns) 0.783 ns CLK 1 CLK Unassigned 1 " "Info: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.235 ns) + CELL(0.000 ns) 1.018 ns CLK~clkctrl 2 COMB Unassigned 452 " "Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 452; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.235 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 2.608 ns R\[0\]\[2\] 3 REG Unassigned 3 " "Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.608 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'R\[0\]\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { CLK~clkctrl R[0][2] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 53.11 % ) " "Info: Total cell delay = 1.385 ns ( 53.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.223 ns ( 46.89 % ) " "Info: Total interconnect delay = 1.223 ns ( 46.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 2 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns   " "Info:   Micro clock to output delay of source is 0.277 ns" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns   " "Info:   Micro setup delay of destination is -0.038 ns" {  } { { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.034 ns - Longest register register " "Info: - Longest register to register delay is 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns R\[0\]\[2\] 1 REG Unassigned 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'R\[0\]\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R[0][2] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.178 ns) 1.280 ns Mux13~0 2 COMB Unassigned 1 " "Info: 2: + IC(1.102 ns) + CELL(0.178 ns) = 1.280 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Mux13~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { R[0][2] Mux13~0 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(0.319 ns) 2.495 ns Mux13~1 3 COMB Unassigned 3 " "Info: 3: + IC(0.896 ns) + CELL(0.319 ns) = 2.495 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'Mux13~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { Mux13~0 Mux13~1 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 4.063 ns Add1~7 4 COMB Unassigned 2 " "Info: 4: + IC(1.073 ns) + CELL(0.495 ns) = 4.063 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~7'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Mux13~1 Add1~7 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.143 ns Add1~10 5 COMB Unassigned 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 4.143 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~10'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~7 Add1~10 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.223 ns Add1~13 6 COMB Unassigned 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.223 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~13'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~10 Add1~13 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.303 ns Add1~16 7 COMB Unassigned 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.303 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~16'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~13 Add1~16 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.383 ns Add1~19 8 COMB Unassigned 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.383 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~19'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~16 Add1~19 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.463 ns Add1~22 9 COMB Unassigned 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 4.463 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~22'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~19 Add1~22 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.543 ns Add1~25 10 COMB Unassigned 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.543 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~25'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~22 Add1~25 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.623 ns Add1~28 11 COMB Unassigned 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 4.623 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~28'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~25 Add1~28 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.703 ns Add1~31 12 COMB Unassigned 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.703 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~31'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~28 Add1~31 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.783 ns Add1~34 13 COMB Unassigned 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.783 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~34'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~31 Add1~34 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.863 ns Add1~37 14 COMB Unassigned 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.863 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~37'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~34 Add1~37 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.943 ns Add1~40 15 COMB Unassigned 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 4.943 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'Add1~40'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~37 Add1~40 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.023 ns Add1~43 16 COMB Unassigned 1 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 5.023 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Add1~43'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~40 Add1~43 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 5.481 ns Add1~45 17 COMB Unassigned 1 " "Info: 17: + IC(0.000 ns) + CELL(0.458 ns) = 5.481 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Add1~45'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Add1~43 Add1~45 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.544 ns) 6.742 ns Add1~47 18 COMB Unassigned 4 " "Info: 18: + IC(0.717 ns) + CELL(0.544 ns) = 6.742 ns; Loc. = Unassigned; Fanout = 4; COMB Node = 'Add1~47'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Add1~45 Add1~47 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.096 ns) 8.034 ns R\[1\]\[15\] 19 REG Unassigned 3 " "Info: 19: + IC(1.196 ns) + CELL(0.096 ns) = 8.034 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'R\[1\]\[15\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.292 ns" { Add1~47 R[1][15] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.050 ns ( 37.96 % ) " "Info: Total cell delay = 3.050 ns ( 37.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.984 ns ( 62.04 % ) " "Info: Total interconnect delay = 4.984 ns ( 62.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { R[0][2] Mux13~0 Mux13~1 Add1~7 Add1~10 Add1~13 Add1~16 Add1~19 Add1~22 Add1~25 Add1~28 Add1~31 Add1~34 Add1~37 Add1~40 Add1~43 Add1~45 Add1~47 R[1][15] } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { R[0][2] Mux13~0 Mux13~1 Add1~7 Add1~10 Add1~13 Add1~16 Add1~19 Add1~22 Add1~25 Add1~28 Add1~31 Add1~34 Add1~37 Add1~40 Add1~43 Add1~45 Add1~47 R[1][15] } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.034 ns register register " "Info: Estimated most critical path is register to register delay of 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns R\[0\]\[2\] 1 REG LAB_X34_Y18 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X34_Y18; Fanout = 3; REG Node = 'R\[0\]\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { R[0][2] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.178 ns) 1.280 ns Mux13~0 2 COMB LAB_X37_Y18 1 " "Info: 2: + IC(1.102 ns) + CELL(0.178 ns) = 1.280 ns; Loc. = LAB_X37_Y18; Fanout = 1; COMB Node = 'Mux13~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { R[0][2] Mux13~0 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(0.319 ns) 2.495 ns Mux13~1 3 COMB LAB_X34_Y18 3 " "Info: 3: + IC(0.896 ns) + CELL(0.319 ns) = 2.495 ns; Loc. = LAB_X34_Y18; Fanout = 3; COMB Node = 'Mux13~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { Mux13~0 Mux13~1 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.495 ns) 4.063 ns Add1~7 4 COMB LAB_X35_Y19 2 " "Info: 4: + IC(1.073 ns) + CELL(0.495 ns) = 4.063 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~7'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { Mux13~1 Add1~7 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.143 ns Add1~10 5 COMB LAB_X35_Y19 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 4.143 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~10'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~7 Add1~10 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.223 ns Add1~13 6 COMB LAB_X35_Y19 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.223 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~13'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~10 Add1~13 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.303 ns Add1~16 7 COMB LAB_X35_Y19 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.303 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~16'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~13 Add1~16 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.383 ns Add1~19 8 COMB LAB_X35_Y19 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.383 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~19'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~16 Add1~19 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.463 ns Add1~22 9 COMB LAB_X35_Y19 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 4.463 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~22'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~19 Add1~22 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.543 ns Add1~25 10 COMB LAB_X35_Y19 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 4.543 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~25'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~22 Add1~25 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.623 ns Add1~28 11 COMB LAB_X35_Y19 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 4.623 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~28'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~25 Add1~28 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.703 ns Add1~31 12 COMB LAB_X35_Y19 2 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 4.703 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~31'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~28 Add1~31 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.783 ns Add1~34 13 COMB LAB_X35_Y19 2 " "Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 4.783 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~34'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~31 Add1~34 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.863 ns Add1~37 14 COMB LAB_X35_Y19 2 " "Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 4.863 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~37'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~34 Add1~37 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.943 ns Add1~40 15 COMB LAB_X35_Y19 2 " "Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 4.943 ns; Loc. = LAB_X35_Y19; Fanout = 2; COMB Node = 'Add1~40'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~37 Add1~40 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.023 ns Add1~43 16 COMB LAB_X35_Y19 1 " "Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 5.023 ns; Loc. = LAB_X35_Y19; Fanout = 1; COMB Node = 'Add1~43'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~40 Add1~43 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 5.481 ns Add1~45 17 COMB LAB_X35_Y19 1 " "Info: 17: + IC(0.000 ns) + CELL(0.458 ns) = 5.481 ns; Loc. = LAB_X35_Y19; Fanout = 1; COMB Node = 'Add1~45'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Add1~43 Add1~45 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.544 ns) 6.742 ns Add1~47 18 COMB LAB_X36_Y17 4 " "Info: 18: + IC(0.717 ns) + CELL(0.544 ns) = 6.742 ns; Loc. = LAB_X36_Y17; Fanout = 4; COMB Node = 'Add1~47'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { Add1~45 Add1~47 } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.096 ns) 8.034 ns R\[1\]\[15\] 19 REG LAB_X36_Y19 3 " "Info: 19: + IC(1.196 ns) + CELL(0.096 ns) = 8.034 ns; Loc. = LAB_X36_Y19; Fanout = 3; REG Node = 'R\[1\]\[15\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.292 ns" { Add1~47 R[1][15] } "NODE_NAME" } } { "SIMCOMP2.v" "" { Text "E:/university/Thirdyear2/DigitalLab/MYWORK/exp11/quartus/SIMCOMP2/SIMCOMP2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.050 ns ( 37.96 % ) " "Info: Total cell delay = 3.050 ns ( 37.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.984 ns ( 62.04 % ) " "Info: Total interconnect delay = 4.984 ns ( 62.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { R[0][2] Mux13~0 Mux13~1 Add1~7 Add1~10 Add1~13 Add1~16 Add1~19 Add1~22 Add1~25 Add1~28 Add1~31 Add1~34 Add1~37 Add1~40 Add1~43 Add1~45 Add1~47 R[1][15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X25_Y14 X37_Y27 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "120 " "Warning: Found 120 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[0\] 0 " "Info: Pin \"PC\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[1\] 0 " "Info: Pin \"PC\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[2\] 0 " "Info: Pin \"PC\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[3\] 0 " "Info: Pin \"PC\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[4\] 0 " "Info: Pin \"PC\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[5\] 0 " "Info: Pin \"PC\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[6\] 0 " "Info: Pin \"PC\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[7\] 0 " "Info: Pin \"PC\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[8\] 0 " "Info: Pin \"PC\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[9\] 0 " "Info: Pin \"PC\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[10\] 0 " "Info: Pin \"PC\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PC\[11\] 0 " "Info: Pin \"PC\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[0\] 0 " "Info: Pin \"R0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[1\] 0 " "Info: Pin \"R0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[2\] 0 " "Info: Pin \"R0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[3\] 0 " "Info: Pin \"R0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[4\] 0 " "Info: Pin \"R0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[5\] 0 " "Info: Pin \"R0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[6\] 0 " "Info: Pin \"R0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[7\] 0 " "Info: Pin \"R0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[8\] 0 " "Info: Pin \"R0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[9\] 0 " "Info: Pin \"R0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[10\] 0 " "Info: Pin \"R0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[11\] 0 " "Info: Pin \"R0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[12\] 0 " "Info: Pin \"R0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[13\] 0 " "Info: Pin \"R0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[14\] 0 " "Info: Pin \"R0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R0\[15\] 0 " "Info: Pin \"R0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[0\] 0 " "Info: Pin \"R1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[1\] 0 " "Info: Pin \"R1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[2\] 0 " "Info: Pin \"R1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[3\] 0 " "Info: Pin \"R1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[4\] 0 " "Info: Pin \"R1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[5\] 0 " "Info: Pin \"R1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[6\] 0 " "Info: Pin \"R1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[7\] 0 " "Info: Pin \"R1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[8\] 0 " "Info: Pin \"R1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[9\] 0 " "Info: Pin \"R1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[10\] 0 " "Info: Pin \"R1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[11\] 0 " "Info: Pin \"R1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[12\] 0 " "Info: Pin \"R1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[13\] 0 " "Info: Pin \"R1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[14\] 0 " "Info: Pin \"R1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R1\[15\] 0 " "Info: Pin \"R1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[0\] 0 " "Info: Pin \"R2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[1\] 0 " "Info: Pin \"R2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[2\] 0 " "Info: Pin \"R2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[3\] 0 " "Info: Pin \"R2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[4\] 0 " "Info: Pin \"R2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[5\] 0 " "Info: Pin \"R2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[6\] 0 " "Info: Pin \"R2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[7\] 0 " "Info: Pin \"R2\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[8\] 0 " "Info: Pin \"R2\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[9\] 0 " "Info: Pin \"R2\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[10\] 0 " "Info: Pin \"R2\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[11\] 0 " "Info: Pin \"R2\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[12\] 0 " "Info: Pin \"R2\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[13\] 0 " "Info: Pin \"R2\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[14\] 0 " "Info: Pin \"R2\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R2\[15\] 0 " "Info: Pin \"R2\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[0\] 0 " "Info: Pin \"R3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[1\] 0 " "Info: Pin \"R3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[2\] 0 " "Info: Pin \"R3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[3\] 0 " "Info: Pin \"R3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[4\] 0 " "Info: Pin \"R3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[5\] 0 " "Info: Pin \"R3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[6\] 0 " "Info: Pin \"R3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[7\] 0 " "Info: Pin \"R3\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[8\] 0 " "Info: Pin \"R3\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[9\] 0 " "Info: Pin \"R3\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[10\] 0 " "Info: Pin \"R3\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[11\] 0 " "Info: Pin \"R3\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[12\] 0 " "Info: Pin \"R3\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[13\] 0 " "Info: Pin \"R3\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[14\] 0 " "Info: Pin \"R3\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R3\[15\] 0 " "Info: Pin \"R3\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[0\] 0 " "Info: Pin \"IR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[1\] 0 " "Info: Pin \"IR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[2\] 0 " "Info: Pin \"IR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[3\] 0 " "Info: Pin \"IR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[4\] 0 " "Info: Pin \"IR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[5\] 0 " "Info: Pin \"IR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[6\] 0 " "Info: Pin \"IR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[7\] 0 " "Info: Pin \"IR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[8\] 0 " "Info: Pin \"IR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[9\] 0 " "Info: Pin \"IR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[10\] 0 " "Info: Pin \"IR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[11\] 0 " "Info: Pin \"IR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[12\] 0 " "Info: Pin \"IR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[13\] 0 " "Info: Pin \"IR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[14\] 0 " "Info: Pin \"IR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IR\[15\] 0 " "Info: Pin \"IR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[0\] 0 " "Info: Pin \"MBR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[1\] 0 " "Info: Pin \"MBR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[2\] 0 " "Info: Pin \"MBR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[3\] 0 " "Info: Pin \"MBR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[4\] 0 " "Info: Pin \"MBR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[5\] 0 " "Info: Pin \"MBR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[6\] 0 " "Info: Pin \"MBR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[7\] 0 " "Info: Pin \"MBR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[8\] 0 " "Info: Pin \"MBR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[9\] 0 " "Info: Pin \"MBR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[10\] 0 " "Info: Pin \"MBR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[11\] 0 " "Info: Pin \"MBR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[12\] 0 " "Info: Pin \"MBR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[13\] 0 " "Info: Pin \"MBR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[14\] 0 " "Info: Pin \"MBR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MBR\[15\] 0 " "Info: Pin \"MBR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[0\] 0 " "Info: Pin \"MAR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[1\] 0 " "Info: Pin \"MAR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[2\] 0 " "Info: Pin \"MAR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[3\] 0 " "Info: Pin \"MAR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[4\] 0 " "Info: Pin \"MAR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[5\] 0 " "Info: Pin \"MAR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[6\] 0 " "Info: Pin \"MAR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[7\] 0 " "Info: Pin \"MAR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[8\] 0 " "Info: Pin \"MAR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[9\] 0 " "Info: Pin \"MAR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[10\] 0 " "Info: Pin \"MAR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MAR\[11\] 0 " "Info: Pin \"MAR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "234 " "Info: Peak virtual memory: 234 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 21:46:23 2010 " "Info: Processing ended: Tue Apr 20 21:46:23 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Info: Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
